1/* 2 * Device Tree Include file for Marvell Armada XP family SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 * 46 * Contains definitions specific to the Armada XP MV78230 SoC that are not 47 * common to all Armada XP SoCs. 48 */ 49 50#include "armada-xp.dtsi" 51 52/ { 53 model = "Marvell Armada XP MV78230 SoC"; 54 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; 55 56 aliases { 57 gpio0 = &gpio0; 58 gpio1 = &gpio1; 59 }; 60 61 cpus { 62 #address-cells = <1>; 63 #size-cells = <0>; 64 enable-method = "marvell,armada-xp-smp"; 65 66 cpu@0 { 67 device_type = "cpu"; 68 compatible = "marvell,sheeva-v7"; 69 reg = <0>; 70 clocks = <&cpuclk 0>; 71 clock-latency = <1000000>; 72 }; 73 74 cpu@1 { 75 device_type = "cpu"; 76 compatible = "marvell,sheeva-v7"; 77 reg = <1>; 78 clocks = <&cpuclk 1>; 79 clock-latency = <1000000>; 80 }; 81 }; 82 83 soc { 84 /* 85 * MV78230 has 2 PCIe units Gen2.0: One unit can be 86 * configured as x4 or quad x1 lanes. One unit is 87 * x1 only. 88 */ 89 pciec: pcie@82000000 { 90 compatible = "marvell,armada-xp-pcie"; 91 status = "disabled"; 92 device_type = "pci"; 93 94 #address-cells = <3>; 95 #size-cells = <2>; 96 97 msi-parent = <&mpic>; 98 bus-range = <0x00 0xff>; 99 100 ranges = 101 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ 102 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ 103 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ 104 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ 105 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ 106 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ 107 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ 108 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ 109 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ 110 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ 111 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ 112 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ 113 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ 114 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ 115 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; 116 117 pcie1: pcie@1,0 { 118 device_type = "pci"; 119 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 120 reg = <0x0800 0 0 0 0>; 121 #address-cells = <3>; 122 #size-cells = <2>; 123 #interrupt-cells = <1>; 124 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 125 0x81000000 0 0 0x81000000 0x1 0 1 0>; 126 bus-range = <0x00 0xff>; 127 interrupt-map-mask = <0 0 0 0>; 128 interrupt-map = <0 0 0 0 &mpic 58>; 129 marvell,pcie-port = <0>; 130 marvell,pcie-lane = <0>; 131 clocks = <&gateclk 5>; 132 status = "disabled"; 133 }; 134 135 pcie2: pcie@2,0 { 136 device_type = "pci"; 137 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 138 reg = <0x1000 0 0 0 0>; 139 #address-cells = <3>; 140 #size-cells = <2>; 141 #interrupt-cells = <1>; 142 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 143 0x81000000 0 0 0x81000000 0x2 0 1 0>; 144 bus-range = <0x00 0xff>; 145 interrupt-map-mask = <0 0 0 0>; 146 interrupt-map = <0 0 0 0 &mpic 59>; 147 marvell,pcie-port = <0>; 148 marvell,pcie-lane = <1>; 149 clocks = <&gateclk 6>; 150 status = "disabled"; 151 }; 152 153 pcie3: pcie@3,0 { 154 device_type = "pci"; 155 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; 156 reg = <0x1800 0 0 0 0>; 157 #address-cells = <3>; 158 #size-cells = <2>; 159 #interrupt-cells = <1>; 160 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 161 0x81000000 0 0 0x81000000 0x3 0 1 0>; 162 bus-range = <0x00 0xff>; 163 interrupt-map-mask = <0 0 0 0>; 164 interrupt-map = <0 0 0 0 &mpic 60>; 165 marvell,pcie-port = <0>; 166 marvell,pcie-lane = <2>; 167 clocks = <&gateclk 7>; 168 status = "disabled"; 169 }; 170 171 pcie4: pcie@4,0 { 172 device_type = "pci"; 173 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; 174 reg = <0x2000 0 0 0 0>; 175 #address-cells = <3>; 176 #size-cells = <2>; 177 #interrupt-cells = <1>; 178 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 179 0x81000000 0 0 0x81000000 0x4 0 1 0>; 180 bus-range = <0x00 0xff>; 181 interrupt-map-mask = <0 0 0 0>; 182 interrupt-map = <0 0 0 0 &mpic 61>; 183 marvell,pcie-port = <0>; 184 marvell,pcie-lane = <3>; 185 clocks = <&gateclk 8>; 186 status = "disabled"; 187 }; 188 189 pcie5: pcie@5,0 { 190 device_type = "pci"; 191 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 192 reg = <0x2800 0 0 0 0>; 193 #address-cells = <3>; 194 #size-cells = <2>; 195 #interrupt-cells = <1>; 196 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 197 0x81000000 0 0 0x81000000 0x5 0 1 0>; 198 bus-range = <0x00 0xff>; 199 interrupt-map-mask = <0 0 0 0>; 200 interrupt-map = <0 0 0 0 &mpic 62>; 201 marvell,pcie-port = <1>; 202 marvell,pcie-lane = <0>; 203 clocks = <&gateclk 9>; 204 status = "disabled"; 205 }; 206 }; 207 208 internal-regs { 209 gpio0: gpio@18100 { 210 compatible = "marvell,orion-gpio"; 211 reg = <0x18100 0x40>; 212 ngpios = <32>; 213 gpio-controller; 214 #gpio-cells = <2>; 215 interrupt-controller; 216 #interrupt-cells = <2>; 217 interrupts = <82>, <83>, <84>, <85>; 218 }; 219 220 gpio1: gpio@18140 { 221 compatible = "marvell,orion-gpio"; 222 reg = <0x18140 0x40>; 223 ngpios = <17>; 224 gpio-controller; 225 #gpio-cells = <2>; 226 interrupt-controller; 227 #interrupt-cells = <2>; 228 interrupts = <87>, <88>, <89>; 229 }; 230 }; 231 }; 232}; 233 234&pinctrl { 235 compatible = "marvell,mv78230-pinctrl"; 236}; 237