1/* 2 * Device Tree file for Marvell Armada XP development board 3 * (DB-MV784MP-GP) 4 * 5 * Copyright (C) 2013-2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 * 11 * This file is dual-licensed: you can use it either under the terms 12 * of the GPL or the X11 license, at your option. Note that this dual 13 * licensing only applies to this file, and not this project as a 14 * whole. 15 * 16 * a) This file is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of the 19 * License, or (at your option) any later version. 20 * 21 * This file is distributed in the hope that it will be useful 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * Or, alternatively 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 * 49 * Note: this Device Tree assumes that the bootloader has remapped the 50 * internal registers to 0xf1000000 (instead of the default 51 * 0xd0000000). The 0xf1000000 is the default used by the recent, 52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 53 * boards were delivered with an older version of the bootloader that 54 * left internal registers mapped at 0xd0000000. If you are in this 55 * situation, you should either update your bootloader (preferred 56 * solution) or the below Device Tree should be adjusted. 57 */ 58 59/dts-v1/; 60#include <dt-bindings/gpio/gpio.h> 61#include "armada-xp-mv78460.dtsi" 62 63/ { 64 model = "Marvell Armada XP Development Board DB-MV784MP-GP"; 65 compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 66 67 chosen { 68 stdout-path = "serial0:115200n8"; 69 }; 70 71 memory { 72 device_type = "memory"; 73 /* 74 * 8 GB of plug-in RAM modules by default.The amount 75 * of memory available can be changed by the 76 * bootloader according the size of the module 77 * actually plugged. However, memory between 78 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is 79 * the address range used for I/O (internal registers, 80 * MBus windows). 81 */ 82 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>, 83 <0x00000001 0x00000000 0x00000001 0x00000000>; 84 }; 85 86 cpus { 87 pm_pic { 88 ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, 89 <&gpio0 17 GPIO_ACTIVE_LOW>, 90 <&gpio0 18 GPIO_ACTIVE_LOW>; 91 }; 92 }; 93 94 soc { 95 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 96 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 97 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; 98 99 devbus-bootcs { 100 status = "okay"; 101 102 /* Device Bus parameters are required */ 103 104 /* Read parameters */ 105 devbus,bus-width = <16>; 106 devbus,turn-off-ps = <60000>; 107 devbus,badr-skew-ps = <0>; 108 devbus,acc-first-ps = <124000>; 109 devbus,acc-next-ps = <248000>; 110 devbus,rd-setup-ps = <0>; 111 devbus,rd-hold-ps = <0>; 112 113 /* Write parameters */ 114 devbus,sync-enable = <0>; 115 devbus,wr-high-ps = <60000>; 116 devbus,wr-low-ps = <60000>; 117 devbus,ale-wr-ps = <60000>; 118 119 /* NOR 16 MiB */ 120 nor@0 { 121 compatible = "cfi-flash"; 122 reg = <0 0x1000000>; 123 bank-width = <2>; 124 }; 125 }; 126 127 pcie-controller { 128 status = "okay"; 129 130 /* 131 * The 3 slots are physically present as 132 * standard PCIe slots on the board. 133 */ 134 pcie@1,0 { 135 /* Port 0, Lane 0 */ 136 status = "okay"; 137 }; 138 pcie@9,0 { 139 /* Port 2, Lane 0 */ 140 status = "okay"; 141 }; 142 pcie@10,0 { 143 /* Port 3, Lane 0 */ 144 status = "okay"; 145 }; 146 }; 147 148 internal-regs { 149 serial@12000 { 150 status = "okay"; 151 }; 152 serial@12100 { 153 status = "okay"; 154 }; 155 serial@12200 { 156 status = "okay"; 157 }; 158 serial@12300 { 159 status = "okay"; 160 }; 161 pinctrl { 162 pinctrl-0 = <&pic_pins>; 163 pinctrl-names = "default"; 164 pic_pins: pic-pins-0 { 165 marvell,pins = "mpp16", "mpp17", 166 "mpp18"; 167 marvell,function = "gpio"; 168 }; 169 }; 170 sata@a0000 { 171 nr-ports = <2>; 172 status = "okay"; 173 }; 174 175 mdio { 176 phy0: ethernet-phy@0 { 177 reg = <16>; 178 }; 179 180 phy1: ethernet-phy@1 { 181 reg = <17>; 182 }; 183 184 phy2: ethernet-phy@2 { 185 reg = <18>; 186 }; 187 188 phy3: ethernet-phy@3 { 189 reg = <19>; 190 }; 191 }; 192 193 ethernet@70000 { 194 status = "okay"; 195 phy = <&phy0>; 196 phy-mode = "qsgmii"; 197 }; 198 ethernet@74000 { 199 status = "okay"; 200 phy = <&phy1>; 201 phy-mode = "qsgmii"; 202 }; 203 ethernet@30000 { 204 status = "okay"; 205 phy = <&phy2>; 206 phy-mode = "qsgmii"; 207 }; 208 ethernet@34000 { 209 status = "okay"; 210 phy = <&phy3>; 211 phy-mode = "qsgmii"; 212 }; 213 214 /* Front-side USB slot */ 215 usb@50000 { 216 status = "okay"; 217 }; 218 219 /* Back-side USB slot */ 220 usb@51000 { 221 status = "okay"; 222 }; 223 224 spi0: spi@10600 { 225 status = "okay"; 226 227 spi-flash@0 { 228 #address-cells = <1>; 229 #size-cells = <1>; 230 compatible = "n25q128a13", "jedec,spi-nor"; 231 reg = <0>; /* Chip select 0 */ 232 spi-max-frequency = <108000000>; 233 }; 234 }; 235 236 nand@d0000 { 237 status = "okay"; 238 num-cs = <1>; 239 marvell,nand-keep-config; 240 marvell,nand-enable-arbiter; 241 nand-on-flash-bbt; 242 }; 243 }; 244 }; 245}; 246