1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada CP110 Slave. 45 */ 46 47#include <dt-bindings/comphy/comphy_data.h> 48 49/ { 50 cp110-slave { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 compatible = "simple-bus"; 54 interrupt-parent = <&gic>; 55 ranges; 56 57 config-space { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 interrupt-parent = <&gic>; 62 ranges = <0x0 0x0 0xf4000000 0x2000000>; 63 64 cps_syscon0: system-controller@440000 { 65 compatible = "marvell,cp110-system-controller0", 66 "syscon"; 67 reg = <0x440000 0x1000>; 68 #clock-cells = <2>; 69 core-clock-output-names = 70 "cps-apll", "cps-ppv2-core", "cps-eip", 71 "cps-core", "cps-nand-core"; 72 gate-clock-output-names = 73 "cps-audio", "cps-communit", "cps-nand", 74 "cps-ppv2", "cps-sdio", "cps-mg-domain", 75 "cps-mg-core", "cps-xor1", "cps-xor0", 76 "cps-gop-dp", "none", "cps-pcie_x10", 77 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", 78 "cps-sata", "cps-sata-usb", "cps-main", 79 "cps-sd-mmc", "none", "none", 80 "cps-slow-io", "cps-usb3h0", "cps-usb3h1", 81 "cps-usb3dev", "cps-eip150", "cps-eip197"; 82 }; 83 84 cps_sata0: sata@540000 { 85 compatible = "marvell,armada-8k-ahci"; 86 reg = <0x540000 0x30000>; 87 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 88 clocks = <&cps_syscon0 1 15>; 89 status = "disabled"; 90 }; 91 92 cps_usb3_0: usb3@500000 { 93 compatible = "marvell,armada-8k-xhci", 94 "generic-xhci"; 95 reg = <0x500000 0x4000>; 96 dma-coherent; 97 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&cps_syscon0 1 22>; 99 status = "disabled"; 100 }; 101 102 cps_usb3_1: usb3@510000 { 103 compatible = "marvell,armada-8k-xhci", 104 "generic-xhci"; 105 reg = <0x510000 0x4000>; 106 dma-coherent; 107 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&cps_syscon0 1 23>; 109 status = "disabled"; 110 }; 111 112 cps_xor0: xor@6a0000 { 113 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 114 reg = <0x6a0000 0x1000>, 115 <0x6b0000 0x1000>; 116 dma-coherent; 117 msi-parent = <&gic_v2m0>; 118 clocks = <&cps_syscon0 1 8>; 119 }; 120 121 cps_xor1: xor@6c0000 { 122 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 123 reg = <0x6c0000 0x1000>, 124 <0x6d0000 0x1000>; 125 dma-coherent; 126 msi-parent = <&gic_v2m0>; 127 clocks = <&cps_syscon0 1 7>; 128 }; 129 130 cps_spi0: spi@700600 { 131 compatible = "marvell,armada-380-spi"; 132 reg = <0x700600 0x50>; 133 #address-cells = <0x1>; 134 #size-cells = <0x0>; 135 cell-index = <1>; 136 clocks = <&cps_syscon0 0 3>; 137 status = "disabled"; 138 }; 139 140 cps_spi1: spi@700680 { 141 compatible = "marvell,armada-380-spi"; 142 reg = <0x700680 0x50>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 cell-index = <2>; 146 clocks = <&cps_syscon0 1 21>; 147 status = "disabled"; 148 }; 149 150 cps_i2c0: i2c@701000 { 151 compatible = "marvell,mv78230-i2c"; 152 reg = <0x701000 0x20>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&cps_syscon0 1 21>; 157 status = "disabled"; 158 }; 159 160 cps_i2c1: i2c@701100 { 161 compatible = "marvell,mv78230-i2c"; 162 reg = <0x701100 0x20>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&cps_syscon0 1 21>; 167 status = "disabled"; 168 }; 169 170 cps_comphy: comphy@441000 { 171 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; 172 reg = <0x441000 0x8>, 173 <0x120000 0x8>; 174 mux-bitcount = <4>; 175 max-lanes = <6>; 176 }; 177 178 cps_utmi0: utmi@580000 { 179 compatible = "marvell,mvebu-utmi-2.6.0"; 180 reg = <0x580000 0x1000>, /* utmi-unit */ 181 <0x440420 0x4>, /* usb-cfg */ 182 <0x440440 0x4>; /* utmi-cfg */ 183 utmi-port = <UTMI_PHY_TO_USB_HOST0>; 184 status = "disabled"; 185 }; 186 }; 187 188 cps_pcie0: pcie@f4600000 { 189 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 190 reg = <0 0xf4600000 0 0x10000>, 191 <0 0xfaf00000 0 0x80000>; 192 reg-names = "ctrl", "config"; 193 #address-cells = <3>; 194 #size-cells = <2>; 195 #interrupt-cells = <1>; 196 device_type = "pci"; 197 dma-coherent; 198 msi-parent = <&gic_v2m0>; 199 200 bus-range = <0 0xff>; 201 ranges = 202 /* downstream I/O */ 203 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 204 /* non-prefetchable memory */ 205 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; 206 interrupt-map-mask = <0 0 0 0>; 207 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 208 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 209 num-lanes = <1>; 210 clocks = <&cps_syscon0 1 13>; 211 status = "disabled"; 212 }; 213 214 cps_pcie1: pcie@f4620000 { 215 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 216 reg = <0 0xf4620000 0 0x10000>, 217 <0 0xfbf00000 0 0x80000>; 218 reg-names = "ctrl", "config"; 219 #address-cells = <3>; 220 #size-cells = <2>; 221 #interrupt-cells = <1>; 222 device_type = "pci"; 223 dma-coherent; 224 msi-parent = <&gic_v2m0>; 225 226 bus-range = <0 0xff>; 227 ranges = 228 /* downstream I/O */ 229 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 230 /* non-prefetchable memory */ 231 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; 232 interrupt-map-mask = <0 0 0 0>; 233 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 234 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 235 236 num-lanes = <1>; 237 clocks = <&cps_syscon0 1 11>; 238 status = "disabled"; 239 }; 240 241 cps_pcie2: pcie@f4640000 { 242 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 243 reg = <0 0xf4640000 0 0x10000>, 244 <0 0xfcf00000 0 0x80000>; 245 reg-names = "ctrl", "config"; 246 #address-cells = <3>; 247 #size-cells = <2>; 248 #interrupt-cells = <1>; 249 device_type = "pci"; 250 dma-coherent; 251 msi-parent = <&gic_v2m0>; 252 253 bus-range = <0 0xff>; 254 ranges = 255 /* downstream I/O */ 256 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 257 /* non-prefetchable memory */ 258 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; 259 interrupt-map-mask = <0 0 0 0>; 260 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 261 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 262 263 num-lanes = <1>; 264 clocks = <&cps_syscon0 1 12>; 265 status = "disabled"; 266 }; 267 }; 268}; 269