1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada CP110 Slave. 45 */ 46 47#include <dt-bindings/comphy/comphy_data.h> 48 49/ { 50 cp110-slave { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 compatible = "simple-bus"; 54 interrupt-parent = <&gic>; 55 ranges; 56 57 config-space { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 interrupt-parent = <&gic>; 62 ranges = <0x0 0x0 0xf4000000 0x2000000>; 63 64 cps_syscon0: system-controller@440000 { 65 compatible = "marvell,cp110-system-controller0", 66 "syscon"; 67 reg = <0x440000 0x1000>; 68 #clock-cells = <2>; 69 core-clock-output-names = 70 "cps-apll", "cps-ppv2-core", "cps-eip", 71 "cps-core", "cps-nand-core"; 72 gate-clock-output-names = 73 "cps-audio", "cps-communit", "cps-nand", 74 "cps-ppv2", "cps-sdio", "cps-mg-domain", 75 "cps-mg-core", "cps-xor1", "cps-xor0", 76 "cps-gop-dp", "none", "cps-pcie_x10", 77 "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor", 78 "cps-sata", "cps-sata-usb", "cps-main", 79 "cps-sd-mmc", "none", "none", 80 "cps-slow-io", "cps-usb3h0", "cps-usb3h1", 81 "cps-usb3dev", "cps-eip150", "cps-eip197"; 82 }; 83 84 cps_pinctl: cps-pinctl@440000 { 85 compatible = "marvell,mvebu-pinctrl", 86 "marvell,a80x0-cp1-pinctrl"; 87 bank-name ="cp1-110"; 88 reg = <0x440000 0x20>; 89 pin-count = <63>; 90 max-func = <0xf>; 91 92 cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 { 93 marvell,pins = < 0 1 2 3 4 5 6 7 94 8 9 10 11 >; 95 marvell,function = <3>; 96 }; 97 cps_spi1_pins: cps-spi-pins-1 { 98 marvell,pins = < 13 14 15 16 >; 99 marvell,function = <3>; 100 }; 101 }; 102 103 cps_sata0: sata@540000 { 104 compatible = "marvell,armada-8k-ahci"; 105 reg = <0x540000 0x30000>; 106 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&cps_syscon0 1 15>; 108 status = "disabled"; 109 }; 110 111 cps_usb3_0: usb3@500000 { 112 compatible = "marvell,armada-8k-xhci", 113 "generic-xhci"; 114 reg = <0x500000 0x4000>; 115 dma-coherent; 116 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&cps_syscon0 1 22>; 118 status = "disabled"; 119 }; 120 121 cps_usb3_1: usb3@510000 { 122 compatible = "marvell,armada-8k-xhci", 123 "generic-xhci"; 124 reg = <0x510000 0x4000>; 125 dma-coherent; 126 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&cps_syscon0 1 23>; 128 status = "disabled"; 129 }; 130 131 cps_xor0: xor@6a0000 { 132 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 133 reg = <0x6a0000 0x1000>, 134 <0x6b0000 0x1000>; 135 dma-coherent; 136 msi-parent = <&gic_v2m0>; 137 clocks = <&cps_syscon0 1 8>; 138 }; 139 140 cps_xor1: xor@6c0000 { 141 compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 142 reg = <0x6c0000 0x1000>, 143 <0x6d0000 0x1000>; 144 dma-coherent; 145 msi-parent = <&gic_v2m0>; 146 clocks = <&cps_syscon0 1 7>; 147 }; 148 149 cps_spi0: spi@700600 { 150 compatible = "marvell,armada-380-spi"; 151 reg = <0x700600 0x50>; 152 #address-cells = <0x1>; 153 #size-cells = <0x0>; 154 cell-index = <1>; 155 clocks = <&cps_syscon0 0 3>; 156 status = "disabled"; 157 }; 158 159 cps_spi1: spi@700680 { 160 compatible = "marvell,armada-380-spi"; 161 reg = <0x700680 0x50>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 cell-index = <2>; 165 clocks = <&cps_syscon0 1 21>; 166 status = "disabled"; 167 }; 168 169 cps_i2c0: i2c@701000 { 170 compatible = "marvell,mv78230-i2c"; 171 reg = <0x701000 0x20>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&cps_syscon0 1 21>; 176 status = "disabled"; 177 }; 178 179 cps_i2c1: i2c@701100 { 180 compatible = "marvell,mv78230-i2c"; 181 reg = <0x701100 0x20>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&cps_syscon0 1 21>; 186 status = "disabled"; 187 }; 188 189 cps_comphy: comphy@441000 { 190 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; 191 reg = <0x441000 0x8>, 192 <0x120000 0x8>; 193 mux-bitcount = <4>; 194 max-lanes = <6>; 195 }; 196 197 cps_utmi0: utmi@580000 { 198 compatible = "marvell,mvebu-utmi-2.6.0"; 199 reg = <0x580000 0x1000>, /* utmi-unit */ 200 <0x440420 0x4>, /* usb-cfg */ 201 <0x440440 0x4>; /* utmi-cfg */ 202 utmi-port = <UTMI_PHY_TO_USB_HOST0>; 203 status = "disabled"; 204 }; 205 }; 206 207 cps_pcie0: pcie@f4600000 { 208 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 209 reg = <0 0xf4600000 0 0x10000>, 210 <0 0xfaf00000 0 0x80000>; 211 reg-names = "ctrl", "config"; 212 #address-cells = <3>; 213 #size-cells = <2>; 214 #interrupt-cells = <1>; 215 device_type = "pci"; 216 dma-coherent; 217 msi-parent = <&gic_v2m0>; 218 219 bus-range = <0 0xff>; 220 ranges = 221 /* downstream I/O */ 222 <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000 223 /* non-prefetchable memory */ 224 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>; 225 interrupt-map-mask = <0 0 0 0>; 226 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 227 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 228 num-lanes = <1>; 229 clocks = <&cps_syscon0 1 13>; 230 status = "disabled"; 231 }; 232 233 cps_pcie1: pcie@f4620000 { 234 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 235 reg = <0 0xf4620000 0 0x10000>, 236 <0 0xfbf00000 0 0x80000>; 237 reg-names = "ctrl", "config"; 238 #address-cells = <3>; 239 #size-cells = <2>; 240 #interrupt-cells = <1>; 241 device_type = "pci"; 242 dma-coherent; 243 msi-parent = <&gic_v2m0>; 244 245 bus-range = <0 0xff>; 246 ranges = 247 /* downstream I/O */ 248 <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000 249 /* non-prefetchable memory */ 250 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>; 251 interrupt-map-mask = <0 0 0 0>; 252 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 253 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 254 255 num-lanes = <1>; 256 clocks = <&cps_syscon0 1 11>; 257 status = "disabled"; 258 }; 259 260 cps_pcie2: pcie@f4640000 { 261 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 262 reg = <0 0xf4640000 0 0x10000>, 263 <0 0xfcf00000 0 0x80000>; 264 reg-names = "ctrl", "config"; 265 #address-cells = <3>; 266 #size-cells = <2>; 267 #interrupt-cells = <1>; 268 device_type = "pci"; 269 dma-coherent; 270 msi-parent = <&gic_v2m0>; 271 272 bus-range = <0 0xff>; 273 ranges = 274 /* downstream I/O */ 275 <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000 276 /* non-prefetchable memory */ 277 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>; 278 interrupt-map-mask = <0 0 0 0>; 279 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 280 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 281 282 num-lanes = <1>; 283 clocks = <&cps_syscon0 1 12>; 284 status = "disabled"; 285 }; 286 }; 287}; 288