1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada CP110 Master. 45 */ 46 47#include <dt-bindings/comphy/comphy_data.h> 48 49/ { 50 cp110-master { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 compatible = "simple-bus"; 54 interrupt-parent = <&gic>; 55 ranges; 56 57 config-space { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 interrupt-parent = <&gic>; 62 ranges = <0x0 0x0 0xf2000000 0x2000000>; 63 64 cpm_syscon0: system-controller@440000 { 65 compatible = "marvell,cp110-system-controller0", 66 "syscon"; 67 reg = <0x440000 0x1000>; 68 #clock-cells = <2>; 69 core-clock-output-names = 70 "cpm-apll", "cpm-ppv2-core", "cpm-eip", 71 "cpm-core", "cpm-nand-core"; 72 gate-clock-output-names = 73 "cpm-audio", "cpm-communit", "cpm-nand", 74 "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", 75 "cpm-mg-core", "cpm-xor1", "cpm-xor0", 76 "cpm-gop-dp", "none", "cpm-pcie_x10", 77 "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", 78 "cpm-sata", "cpm-sata-usb", "cpm-main", 79 "cpm-sd-mmc", "none", "none", 80 "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", 81 "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; 82 }; 83 84 cpm_pinctl: cpm-pinctl@440000 { 85 compatible = "marvell,mvebu-pinctrl", 86 "marvell,a70x0-pinctrl", 87 "marvell,a80x0-cp0-pinctrl"; 88 bank-name ="cp0-110"; 89 reg = <0x440000 0x20>; 90 pin-count = <63>; 91 max-func = <0xf>; 92 93 cpm_i2c0_pins: cpm-i2c-pins-0 { 94 marvell,pins = < 37 38 >; 95 marvell,function = <2>; 96 }; 97 cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 { 98 marvell,pins = < 44 45 46 47 48 49 50 51 99 52 53 54 55 >; 100 marvell,function = <1>; 101 }; 102 pca0_pins: cpm-pca0_pins { 103 marvell,pins = <62>; 104 marvell,function = <0>; 105 }; 106 cpm_sdhci_pins: cpm-sdhi-pins-0 { 107 marvell,pins = < 56 57 58 59 60 61 >; 108 marvell,function = <14>; 109 }; 110 cpm_spi0_pins: cpm-spi-pins-0 { 111 marvell,pins = < 13 14 15 16 >; 112 marvell,function = <3>; 113 }; 114 }; 115 116 cpm_sata0: sata@540000 { 117 compatible = "marvell,armada-8k-ahci"; 118 reg = <0x540000 0x30000>; 119 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 120 clocks = <&cpm_syscon0 1 15>; 121 status = "disabled"; 122 }; 123 124 cpm_usb3_0: usb3@500000 { 125 compatible = "marvell,armada-8k-xhci", 126 "generic-xhci"; 127 reg = <0x500000 0x4000>; 128 dma-coherent; 129 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 130 clocks = <&cpm_syscon0 1 22>; 131 status = "disabled"; 132 }; 133 134 cpm_usb3_1: usb3@510000 { 135 compatible = "marvell,armada-8k-xhci", 136 "generic-xhci"; 137 reg = <0x510000 0x4000>; 138 dma-coherent; 139 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 140 clocks = <&cpm_syscon0 1 23>; 141 status = "disabled"; 142 }; 143 144 cpm_spi0: spi@700600 { 145 compatible = "marvell,armada-380-spi"; 146 reg = <0x700600 0x50>; 147 #address-cells = <0x1>; 148 #size-cells = <0x0>; 149 cell-index = <1>; 150 clocks = <&cpm_syscon0 0 3>; 151 status = "disabled"; 152 }; 153 154 cpm_spi1: spi@700680 { 155 compatible = "marvell,armada-380-spi"; 156 reg = <0x700680 0x50>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 cell-index = <2>; 160 clocks = <&cpm_syscon0 1 21>; 161 status = "disabled"; 162 }; 163 164 cpm_i2c0: i2c@701000 { 165 compatible = "marvell,mv78230-i2c"; 166 reg = <0x701000 0x20>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&cpm_syscon0 1 21>; 171 status = "disabled"; 172 }; 173 174 cpm_i2c1: i2c@701100 { 175 compatible = "marvell,mv78230-i2c"; 176 reg = <0x701100 0x20>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cpm_syscon0 1 21>; 181 status = "disabled"; 182 }; 183 184 cpm_comphy: comphy@441000 { 185 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; 186 reg = <0x441000 0x8>, 187 <0x120000 0x8>; 188 mux-bitcount = <4>; 189 max-lanes = <6>; 190 }; 191 192 cpm_utmi0: utmi@580000 { 193 compatible = "marvell,mvebu-utmi-2.6.0"; 194 reg = <0x580000 0x1000>, /* utmi-unit */ 195 <0x440420 0x4>, /* usb-cfg */ 196 <0x440440 0x4>; /* utmi-cfg */ 197 utmi-port = <UTMI_PHY_TO_USB_HOST0>; 198 status = "disabled"; 199 }; 200 201 cpm_utmi1: utmi@581000 { 202 compatible = "marvell,mvebu-utmi-2.6.0"; 203 reg = <0x581000 0x1000>, /* utmi-unit */ 204 <0x440420 0x4>, /* usb-cfg */ 205 <0x440444 0x4>; /* utmi-cfg */ 206 utmi-port = <UTMI_PHY_TO_USB_HOST1>; 207 status = "disabled"; 208 }; 209 210 cpm_sdhci0: sdhci@780000 { 211 compatible = "marvell,armada-8k-sdhci"; 212 reg = <0x780000 0x300>; 213 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 214 dma-coherent; 215 status = "disabled"; 216 }; 217 }; 218 219 cpm_pcie0: pcie@f2600000 { 220 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 221 reg = <0 0xf2600000 0 0x10000>, 222 <0 0xf6f00000 0 0x80000>; 223 reg-names = "ctrl", "config"; 224 #address-cells = <3>; 225 #size-cells = <2>; 226 #interrupt-cells = <1>; 227 device_type = "pci"; 228 dma-coherent; 229 230 bus-range = <0 0xff>; 231 ranges = 232 /* downstream I/O */ 233 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 234 /* non-prefetchable memory */ 235 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; 236 interrupt-map-mask = <0 0 0 0>; 237 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 239 num-lanes = <1>; 240 clocks = <&cpm_syscon0 1 13>; 241 status = "disabled"; 242 }; 243 244 cpm_pcie1: pcie@f2620000 { 245 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 246 reg = <0 0xf2620000 0 0x10000>, 247 <0 0xf7f00000 0 0x80000>; 248 reg-names = "ctrl", "config"; 249 #address-cells = <3>; 250 #size-cells = <2>; 251 #interrupt-cells = <1>; 252 device_type = "pci"; 253 dma-coherent; 254 255 bus-range = <0 0xff>; 256 ranges = 257 /* downstream I/O */ 258 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000 259 /* non-prefetchable memory */ 260 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; 261 interrupt-map-mask = <0 0 0 0>; 262 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 263 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 264 265 num-lanes = <1>; 266 clocks = <&cpm_syscon0 1 11>; 267 status = "disabled"; 268 }; 269 270 cpm_pcie2: pcie@f2640000 { 271 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 272 reg = <0 0xf2640000 0 0x10000>, 273 <0 0xf8f00000 0 0x80000>; 274 reg-names = "ctrl", "config"; 275 #address-cells = <3>; 276 #size-cells = <2>; 277 #interrupt-cells = <1>; 278 device_type = "pci"; 279 dma-coherent; 280 281 bus-range = <0 0xff>; 282 ranges = 283 /* downstream I/O */ 284 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000 285 /* non-prefetchable memory */ 286 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; 287 interrupt-map-mask = <0 0 0 0>; 288 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 289 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 290 291 num-lanes = <1>; 292 clocks = <&cpm_syscon0 1 12>; 293 status = "disabled"; 294 }; 295 }; 296}; 297