1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada CP110 Master. 45 */ 46 47#include <dt-bindings/comphy/comphy_data.h> 48 49/ { 50 cp110-master { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 compatible = "simple-bus"; 54 interrupt-parent = <&gic>; 55 ranges; 56 57 config-space { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "simple-bus"; 61 interrupt-parent = <&gic>; 62 ranges = <0x0 0x0 0xf2000000 0x2000000>; 63 64 cpm_syscon0: system-controller@440000 { 65 compatible = "marvell,cp110-system-controller0", 66 "syscon"; 67 reg = <0x440000 0x1000>; 68 #clock-cells = <2>; 69 core-clock-output-names = 70 "cpm-apll", "cpm-ppv2-core", "cpm-eip", 71 "cpm-core", "cpm-nand-core"; 72 gate-clock-output-names = 73 "cpm-audio", "cpm-communit", "cpm-nand", 74 "cpm-ppv2", "cpm-sdio", "cpm-mg-domain", 75 "cpm-mg-core", "cpm-xor1", "cpm-xor0", 76 "cpm-gop-dp", "none", "cpm-pcie_x10", 77 "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", 78 "cpm-sata", "cpm-sata-usb", "cpm-main", 79 "cpm-sd-mmc", "none", "none", 80 "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1", 81 "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; 82 }; 83 84 cpm_pinctl: cpm-pinctl@440000 { 85 compatible = "marvell,mvebu-pinctrl", 86 "marvell,a70x0-pinctrl", 87 "marvell,a80x0-cp0-pinctrl"; 88 bank-name ="cp0-110"; 89 reg = <0x440000 0x20>; 90 pin-count = <63>; 91 max-func = <0xf>; 92 93 cpm_i2c0_pins: cpm-i2c-pins-0 { 94 marvell,pins = < 37 38 >; 95 marvell,function = <2>; 96 }; 97 cpm_i2c1_pins: cpm-i2c-pins-1 { 98 marvell,pins = < 35 36 >; 99 marvell,function = <2>; 100 }; 101 cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 { 102 marvell,pins = < 44 45 46 47 48 49 50 51 103 52 53 54 55 >; 104 marvell,function = <1>; 105 }; 106 pca0_pins: cpm-pca0_pins { 107 marvell,pins = <62>; 108 marvell,function = <0>; 109 }; 110 cpm_sdhci_pins: cpm-sdhi-pins-0 { 111 marvell,pins = < 56 57 58 59 60 61 >; 112 marvell,function = <14>; 113 }; 114 cpm_spi0_pins: cpm-spi-pins-0 { 115 marvell,pins = < 13 14 15 16 >; 116 marvell,function = <3>; 117 }; 118 }; 119 120 cpm_gpio0: gpio@440100 { 121 compatible = "marvell,orion-gpio"; 122 reg = <0x440100 0x40>; 123 ngpios = <32>; 124 gpiobase = <20>; 125 gpio-controller; 126 #gpio-cells = <2>; 127 }; 128 129 cpm_gpio1: gpio@440140 { 130 compatible = "marvell,orion-gpio"; 131 reg = <0x440140 0x40>; 132 ngpios = <31>; 133 gpiobase = <52>; 134 gpio-controller; 135 #gpio-cells = <2>; 136 }; 137 138 cpm_sata0: sata@540000 { 139 compatible = "marvell,armada-8k-ahci"; 140 reg = <0x540000 0x30000>; 141 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&cpm_syscon0 1 15>; 143 status = "disabled"; 144 }; 145 146 cpm_usb3_0: usb3@500000 { 147 compatible = "marvell,armada-8k-xhci", 148 "generic-xhci"; 149 reg = <0x500000 0x4000>; 150 dma-coherent; 151 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&cpm_syscon0 1 22>; 153 status = "disabled"; 154 }; 155 156 cpm_usb3_1: usb3@510000 { 157 compatible = "marvell,armada-8k-xhci", 158 "generic-xhci"; 159 reg = <0x510000 0x4000>; 160 dma-coherent; 161 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&cpm_syscon0 1 23>; 163 status = "disabled"; 164 }; 165 166 cpm_spi0: spi@700600 { 167 compatible = "marvell,armada-380-spi"; 168 reg = <0x700600 0x50>; 169 #address-cells = <0x1>; 170 #size-cells = <0x0>; 171 cell-index = <1>; 172 clocks = <&cpm_syscon0 0 3>; 173 status = "disabled"; 174 }; 175 176 cpm_spi1: spi@700680 { 177 compatible = "marvell,armada-380-spi"; 178 reg = <0x700680 0x50>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 cell-index = <2>; 182 clocks = <&cpm_syscon0 1 21>; 183 status = "disabled"; 184 }; 185 186 cpm_i2c0: i2c@701000 { 187 compatible = "marvell,mv78230-i2c"; 188 reg = <0x701000 0x20>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 192 clocks = <&cpm_syscon0 1 21>; 193 status = "disabled"; 194 }; 195 196 cpm_i2c1: i2c@701100 { 197 compatible = "marvell,mv78230-i2c"; 198 reg = <0x701100 0x20>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cpm_syscon0 1 21>; 203 status = "disabled"; 204 }; 205 206 cpm_comphy: comphy@441000 { 207 compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; 208 reg = <0x441000 0x8>, 209 <0x120000 0x8>; 210 mux-bitcount = <4>; 211 max-lanes = <6>; 212 }; 213 214 cpm_utmi0: utmi@580000 { 215 compatible = "marvell,mvebu-utmi-2.6.0"; 216 reg = <0x580000 0x1000>, /* utmi-unit */ 217 <0x440420 0x4>, /* usb-cfg */ 218 <0x440440 0x4>; /* utmi-cfg */ 219 utmi-port = <UTMI_PHY_TO_USB_HOST0>; 220 status = "disabled"; 221 }; 222 223 cpm_utmi1: utmi@581000 { 224 compatible = "marvell,mvebu-utmi-2.6.0"; 225 reg = <0x581000 0x1000>, /* utmi-unit */ 226 <0x440420 0x4>, /* usb-cfg */ 227 <0x440444 0x4>; /* utmi-cfg */ 228 utmi-port = <UTMI_PHY_TO_USB_HOST1>; 229 status = "disabled"; 230 }; 231 232 cpm_sdhci0: sdhci@780000 { 233 compatible = "marvell,armada-8k-sdhci"; 234 reg = <0x780000 0x300>; 235 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 236 dma-coherent; 237 status = "disabled"; 238 }; 239 }; 240 241 cpm_pcie0: pcie@f2600000 { 242 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 243 reg = <0 0xf2600000 0 0x10000>, 244 <0 0xf6f00000 0 0x80000>; 245 reg-names = "ctrl", "config"; 246 #address-cells = <3>; 247 #size-cells = <2>; 248 #interrupt-cells = <1>; 249 device_type = "pci"; 250 dma-coherent; 251 252 bus-range = <0 0xff>; 253 ranges = 254 /* downstream I/O */ 255 <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 256 /* non-prefetchable memory */ 257 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; 258 interrupt-map-mask = <0 0 0 0>; 259 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 260 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 261 num-lanes = <1>; 262 clocks = <&cpm_syscon0 1 13>; 263 status = "disabled"; 264 }; 265 266 cpm_pcie1: pcie@f2620000 { 267 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 268 reg = <0 0xf2620000 0 0x10000>, 269 <0 0xf7f00000 0 0x80000>; 270 reg-names = "ctrl", "config"; 271 #address-cells = <3>; 272 #size-cells = <2>; 273 #interrupt-cells = <1>; 274 device_type = "pci"; 275 dma-coherent; 276 277 bus-range = <0 0xff>; 278 ranges = 279 /* downstream I/O */ 280 <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000 281 /* non-prefetchable memory */ 282 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>; 283 interrupt-map-mask = <0 0 0 0>; 284 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 285 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 286 287 num-lanes = <1>; 288 clocks = <&cpm_syscon0 1 11>; 289 status = "disabled"; 290 }; 291 292 cpm_pcie2: pcie@f2640000 { 293 compatible = "marvell,armada8k-pcie", "snps,dw-pcie"; 294 reg = <0 0xf2640000 0 0x10000>, 295 <0 0xf8f00000 0 0x80000>; 296 reg-names = "ctrl", "config"; 297 #address-cells = <3>; 298 #size-cells = <2>; 299 #interrupt-cells = <1>; 300 device_type = "pci"; 301 dma-coherent; 302 303 bus-range = <0 0xff>; 304 ranges = 305 /* downstream I/O */ 306 <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000 307 /* non-prefetchable memory */ 308 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>; 309 interrupt-map-mask = <0 0 0 0>; 310 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 311 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 312 313 num-lanes = <1>; 314 clocks = <&cpm_syscon0 1 12>; 315 status = "disabled"; 316 }; 317 }; 318}; 319