1*1335483aSStefan Roese/* 2*1335483aSStefan Roese * Copyright (C) 2016 Marvell Technology Group Ltd. 3*1335483aSStefan Roese * 4*1335483aSStefan Roese * This file is dual-licensed: you can use it either under the terms 5*1335483aSStefan Roese * of the GPLv2 or the X11 license, at your option. Note that this dual 6*1335483aSStefan Roese * licensing only applies to this file, and not this project as a 7*1335483aSStefan Roese * whole. 8*1335483aSStefan Roese * 9*1335483aSStefan Roese * a) This library is free software; you can redistribute it and/or 10*1335483aSStefan Roese * modify it under the terms of the GNU General Public License as 11*1335483aSStefan Roese * published by the Free Software Foundation; either version 2 of the 12*1335483aSStefan Roese * License, or (at your option) any later version. 13*1335483aSStefan Roese * 14*1335483aSStefan Roese * This library is distributed in the hope that it will be useful, 15*1335483aSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*1335483aSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*1335483aSStefan Roese * GNU General Public License for more details. 18*1335483aSStefan Roese * 19*1335483aSStefan Roese * Or, alternatively, 20*1335483aSStefan Roese * 21*1335483aSStefan Roese * b) Permission is hereby granted, free of charge, to any person 22*1335483aSStefan Roese * obtaining a copy of this software and associated documentation 23*1335483aSStefan Roese * files (the "Software"), to deal in the Software without 24*1335483aSStefan Roese * restriction, including without limitation the rights to use, 25*1335483aSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 26*1335483aSStefan Roese * sell copies of the Software, and to permit persons to whom the 27*1335483aSStefan Roese * Software is furnished to do so, subject to the following 28*1335483aSStefan Roese * conditions: 29*1335483aSStefan Roese * 30*1335483aSStefan Roese * The above copyright notice and this permission notice shall be 31*1335483aSStefan Roese * included in all copies or substantial portions of the Software. 32*1335483aSStefan Roese * 33*1335483aSStefan Roese * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*1335483aSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*1335483aSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*1335483aSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*1335483aSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*1335483aSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*1335483aSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*1335483aSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 41*1335483aSStefan Roese */ 42*1335483aSStefan Roese 43*1335483aSStefan Roese/* 44*1335483aSStefan Roese * Device Tree file for Marvell Armada AP806. 45*1335483aSStefan Roese */ 46*1335483aSStefan Roese 47*1335483aSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 48*1335483aSStefan Roese 49*1335483aSStefan Roese/dts-v1/; 50*1335483aSStefan Roese 51*1335483aSStefan Roese/ { 52*1335483aSStefan Roese model = "Marvell Armada AP806"; 53*1335483aSStefan Roese compatible = "marvell,armada-ap806"; 54*1335483aSStefan Roese #address-cells = <2>; 55*1335483aSStefan Roese #size-cells = <2>; 56*1335483aSStefan Roese 57*1335483aSStefan Roese aliases { 58*1335483aSStefan Roese serial0 = &uart0; 59*1335483aSStefan Roese serial1 = &uart1; 60*1335483aSStefan Roese }; 61*1335483aSStefan Roese 62*1335483aSStefan Roese psci { 63*1335483aSStefan Roese compatible = "arm,psci-0.2"; 64*1335483aSStefan Roese method = "smc"; 65*1335483aSStefan Roese }; 66*1335483aSStefan Roese 67*1335483aSStefan Roese ap806 { 68*1335483aSStefan Roese #address-cells = <2>; 69*1335483aSStefan Roese #size-cells = <2>; 70*1335483aSStefan Roese compatible = "simple-bus"; 71*1335483aSStefan Roese interrupt-parent = <&gic>; 72*1335483aSStefan Roese ranges; 73*1335483aSStefan Roese 74*1335483aSStefan Roese config-space { 75*1335483aSStefan Roese #address-cells = <1>; 76*1335483aSStefan Roese #size-cells = <1>; 77*1335483aSStefan Roese compatible = "simple-bus"; 78*1335483aSStefan Roese ranges = <0x0 0x0 0xf0000000 0x1000000>; 79*1335483aSStefan Roese 80*1335483aSStefan Roese gic: interrupt-controller@210000 { 81*1335483aSStefan Roese compatible = "arm,gic-400"; 82*1335483aSStefan Roese #interrupt-cells = <3>; 83*1335483aSStefan Roese #address-cells = <1>; 84*1335483aSStefan Roese #size-cells = <1>; 85*1335483aSStefan Roese ranges; 86*1335483aSStefan Roese interrupt-controller; 87*1335483aSStefan Roese interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 88*1335483aSStefan Roese reg = <0x210000 0x10000>, 89*1335483aSStefan Roese <0x220000 0x20000>, 90*1335483aSStefan Roese <0x240000 0x20000>, 91*1335483aSStefan Roese <0x260000 0x20000>; 92*1335483aSStefan Roese 93*1335483aSStefan Roese gic_v2m0: v2m@280000 { 94*1335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 95*1335483aSStefan Roese msi-controller; 96*1335483aSStefan Roese reg = <0x280000 0x1000>; 97*1335483aSStefan Roese arm,msi-base-spi = <160>; 98*1335483aSStefan Roese arm,msi-num-spis = <32>; 99*1335483aSStefan Roese }; 100*1335483aSStefan Roese gic_v2m1: v2m@290000 { 101*1335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 102*1335483aSStefan Roese msi-controller; 103*1335483aSStefan Roese reg = <0x290000 0x1000>; 104*1335483aSStefan Roese arm,msi-base-spi = <192>; 105*1335483aSStefan Roese arm,msi-num-spis = <32>; 106*1335483aSStefan Roese }; 107*1335483aSStefan Roese gic_v2m2: v2m@2a0000 { 108*1335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 109*1335483aSStefan Roese msi-controller; 110*1335483aSStefan Roese reg = <0x2a0000 0x1000>; 111*1335483aSStefan Roese arm,msi-base-spi = <224>; 112*1335483aSStefan Roese arm,msi-num-spis = <32>; 113*1335483aSStefan Roese }; 114*1335483aSStefan Roese gic_v2m3: v2m@2b0000 { 115*1335483aSStefan Roese compatible = "arm,gic-v2m-frame"; 116*1335483aSStefan Roese msi-controller; 117*1335483aSStefan Roese reg = <0x2b0000 0x1000>; 118*1335483aSStefan Roese arm,msi-base-spi = <256>; 119*1335483aSStefan Roese arm,msi-num-spis = <32>; 120*1335483aSStefan Roese }; 121*1335483aSStefan Roese }; 122*1335483aSStefan Roese 123*1335483aSStefan Roese timer { 124*1335483aSStefan Roese compatible = "arm,armv8-timer"; 125*1335483aSStefan Roese interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, 126*1335483aSStefan Roese <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, 127*1335483aSStefan Roese <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>, 128*1335483aSStefan Roese <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 129*1335483aSStefan Roese }; 130*1335483aSStefan Roese 131*1335483aSStefan Roese odmi: odmi@300000 { 132*1335483aSStefan Roese compatible = "marvell,odmi-controller"; 133*1335483aSStefan Roese interrupt-controller; 134*1335483aSStefan Roese msi-controller; 135*1335483aSStefan Roese marvell,odmi-frames = <4>; 136*1335483aSStefan Roese reg = <0x300000 0x4000>, 137*1335483aSStefan Roese <0x304000 0x4000>, 138*1335483aSStefan Roese <0x308000 0x4000>, 139*1335483aSStefan Roese <0x30C000 0x4000>; 140*1335483aSStefan Roese marvell,spi-base = <128>, <136>, <144>, <152>; 141*1335483aSStefan Roese }; 142*1335483aSStefan Roese 143*1335483aSStefan Roese xor@400000 { 144*1335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 145*1335483aSStefan Roese reg = <0x400000 0x1000>, 146*1335483aSStefan Roese <0x410000 0x1000>; 147*1335483aSStefan Roese msi-parent = <&gic_v2m0>; 148*1335483aSStefan Roese dma-coherent; 149*1335483aSStefan Roese }; 150*1335483aSStefan Roese 151*1335483aSStefan Roese xor@420000 { 152*1335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 153*1335483aSStefan Roese reg = <0x420000 0x1000>, 154*1335483aSStefan Roese <0x430000 0x1000>; 155*1335483aSStefan Roese msi-parent = <&gic_v2m0>; 156*1335483aSStefan Roese dma-coherent; 157*1335483aSStefan Roese }; 158*1335483aSStefan Roese 159*1335483aSStefan Roese xor@440000 { 160*1335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 161*1335483aSStefan Roese reg = <0x440000 0x1000>, 162*1335483aSStefan Roese <0x450000 0x1000>; 163*1335483aSStefan Roese msi-parent = <&gic_v2m0>; 164*1335483aSStefan Roese dma-coherent; 165*1335483aSStefan Roese }; 166*1335483aSStefan Roese 167*1335483aSStefan Roese xor@460000 { 168*1335483aSStefan Roese compatible = "marvell,mv-xor-v2"; 169*1335483aSStefan Roese reg = <0x460000 0x1000>, 170*1335483aSStefan Roese <0x470000 0x1000>; 171*1335483aSStefan Roese msi-parent = <&gic_v2m0>; 172*1335483aSStefan Roese dma-coherent; 173*1335483aSStefan Roese }; 174*1335483aSStefan Roese 175*1335483aSStefan Roese spi0: spi@510600 { 176*1335483aSStefan Roese compatible = "marvell,armada-380-spi"; 177*1335483aSStefan Roese reg = <0x510600 0x50>; 178*1335483aSStefan Roese #address-cells = <1>; 179*1335483aSStefan Roese #size-cells = <0>; 180*1335483aSStefan Roese cell-index = <0>; 181*1335483aSStefan Roese interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 182*1335483aSStefan Roese clocks = <&ap_syscon 3>; 183*1335483aSStefan Roese status = "disabled"; 184*1335483aSStefan Roese }; 185*1335483aSStefan Roese 186*1335483aSStefan Roese i2c0: i2c@511000 { 187*1335483aSStefan Roese compatible = "marvell,mv78230-i2c"; 188*1335483aSStefan Roese reg = <0x511000 0x20>; 189*1335483aSStefan Roese #address-cells = <1>; 190*1335483aSStefan Roese #size-cells = <0>; 191*1335483aSStefan Roese interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 192*1335483aSStefan Roese timeout-ms = <1000>; 193*1335483aSStefan Roese clocks = <&ap_syscon 3>; 194*1335483aSStefan Roese status = "disabled"; 195*1335483aSStefan Roese }; 196*1335483aSStefan Roese 197*1335483aSStefan Roese uart0: serial@512000 { 198*1335483aSStefan Roese compatible = "snps,dw-apb-uart"; 199*1335483aSStefan Roese reg = <0x512000 0x100>; 200*1335483aSStefan Roese reg-shift = <2>; 201*1335483aSStefan Roese interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 202*1335483aSStefan Roese reg-io-width = <1>; 203*1335483aSStefan Roese clocks = <&ap_syscon 3>; 204*1335483aSStefan Roese status = "disabled"; 205*1335483aSStefan Roese }; 206*1335483aSStefan Roese 207*1335483aSStefan Roese uart1: serial@512100 { 208*1335483aSStefan Roese compatible = "snps,dw-apb-uart"; 209*1335483aSStefan Roese reg = <0x512100 0x100>; 210*1335483aSStefan Roese reg-shift = <2>; 211*1335483aSStefan Roese interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 212*1335483aSStefan Roese reg-io-width = <1>; 213*1335483aSStefan Roese clocks = <&ap_syscon 3>; 214*1335483aSStefan Roese status = "disabled"; 215*1335483aSStefan Roese 216*1335483aSStefan Roese }; 217*1335483aSStefan Roese 218*1335483aSStefan Roese ap_syscon: system-controller@6f4000 { 219*1335483aSStefan Roese compatible = "marvell,ap806-system-controller", 220*1335483aSStefan Roese "syscon"; 221*1335483aSStefan Roese #clock-cells = <1>; 222*1335483aSStefan Roese clock-output-names = "ap-cpu-cluster-0", 223*1335483aSStefan Roese "ap-cpu-cluster-1", 224*1335483aSStefan Roese "ap-fixed", "ap-mss"; 225*1335483aSStefan Roese reg = <0x6f4000 0x1000>; 226*1335483aSStefan Roese }; 227*1335483aSStefan Roese }; 228*1335483aSStefan Roese }; 229*1335483aSStefan Roese}; 230