1*1335483aSStefan Roese/* 2*1335483aSStefan Roese * Copyright (C) 2016 Marvell Technology Group Ltd. 3*1335483aSStefan Roese * 4*1335483aSStefan Roese * This file is dual-licensed: you can use it either under the terms 5*1335483aSStefan Roese * of the GPLv2 or the X11 license, at your option. Note that this dual 6*1335483aSStefan Roese * licensing only applies to this file, and not this project as a 7*1335483aSStefan Roese * whole. 8*1335483aSStefan Roese * 9*1335483aSStefan Roese * a) This library is free software; you can redistribute it and/or 10*1335483aSStefan Roese * modify it under the terms of the GNU General Public License as 11*1335483aSStefan Roese * published by the Free Software Foundation; either version 2 of the 12*1335483aSStefan Roese * License, or (at your option) any later version. 13*1335483aSStefan Roese * 14*1335483aSStefan Roese * This library is distributed in the hope that it will be useful, 15*1335483aSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 16*1335483aSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17*1335483aSStefan Roese * GNU General Public License for more details. 18*1335483aSStefan Roese * 19*1335483aSStefan Roese * Or, alternatively, 20*1335483aSStefan Roese * 21*1335483aSStefan Roese * b) Permission is hereby granted, free of charge, to any person 22*1335483aSStefan Roese * obtaining a copy of this software and associated documentation 23*1335483aSStefan Roese * files (the "Software"), to deal in the Software without 24*1335483aSStefan Roese * restriction, including without limitation the rights to use, 25*1335483aSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 26*1335483aSStefan Roese * sell copies of the Software, and to permit persons to whom the 27*1335483aSStefan Roese * Software is furnished to do so, subject to the following 28*1335483aSStefan Roese * conditions: 29*1335483aSStefan Roese * 30*1335483aSStefan Roese * The above copyright notice and this permission notice shall be 31*1335483aSStefan Roese * included in all copies or substantial portions of the Software. 32*1335483aSStefan Roese * 33*1335483aSStefan Roese * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34*1335483aSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35*1335483aSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36*1335483aSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37*1335483aSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38*1335483aSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39*1335483aSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40*1335483aSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 41*1335483aSStefan Roese */ 42*1335483aSStefan Roese 43*1335483aSStefan Roese/* 44*1335483aSStefan Roese * Device Tree file for Marvell Armada AP806. 45*1335483aSStefan Roese */ 46*1335483aSStefan Roese 47*1335483aSStefan Roese#include "armada-ap806.dtsi" 48*1335483aSStefan Roese 49*1335483aSStefan Roese/ { 50*1335483aSStefan Roese model = "Marvell Armada AP806 Quad"; 51*1335483aSStefan Roese compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; 52*1335483aSStefan Roese 53*1335483aSStefan Roese cpus { 54*1335483aSStefan Roese #address-cells = <1>; 55*1335483aSStefan Roese #size-cells = <0>; 56*1335483aSStefan Roese 57*1335483aSStefan Roese cpu@000 { 58*1335483aSStefan Roese device_type = "cpu"; 59*1335483aSStefan Roese compatible = "arm,cortex-a72", "arm,armv8"; 60*1335483aSStefan Roese reg = <0x000>; 61*1335483aSStefan Roese enable-method = "psci"; 62*1335483aSStefan Roese }; 63*1335483aSStefan Roese cpu@001 { 64*1335483aSStefan Roese device_type = "cpu"; 65*1335483aSStefan Roese compatible = "arm,cortex-a72", "arm,armv8"; 66*1335483aSStefan Roese reg = <0x001>; 67*1335483aSStefan Roese enable-method = "psci"; 68*1335483aSStefan Roese }; 69*1335483aSStefan Roese cpu@100 { 70*1335483aSStefan Roese device_type = "cpu"; 71*1335483aSStefan Roese compatible = "arm,cortex-a72", "arm,armv8"; 72*1335483aSStefan Roese reg = <0x100>; 73*1335483aSStefan Roese enable-method = "psci"; 74*1335483aSStefan Roese }; 75*1335483aSStefan Roese cpu@101 { 76*1335483aSStefan Roese device_type = "cpu"; 77*1335483aSStefan Roese compatible = "arm,cortex-a72", "arm,armv8"; 78*1335483aSStefan Roese reg = <0x101>; 79*1335483aSStefan Roese enable-method = "psci"; 80*1335483aSStefan Roese }; 81*1335483aSStefan Roese }; 82*1335483aSStefan Roese}; 83