1/* 2 * Copyright (C) 2016 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * https://spdx.org/licenses 6 */ 7 8#include "armada-8040.dtsi" /* include SoC device tree */ 9 10/ { 11 model = "MACCHIATOBin-8040"; 12 compatible = "marvell,armada8040-mcbin", 13 "marvell,armada8040"; 14 15 chosen { 16 stdout-path = "serial0:115200n8"; 17 }; 18 19 aliases { 20 i2c0 = &cpm_i2c0; 21 i2c1 = &cpm_i2c1; 22 spi0 = &cps_spi1; 23 gpio0 = &ap_gpio0; 24 gpio1 = &cpm_gpio0; 25 gpio2 = &cpm_gpio1; 26 }; 27 28 memory@00000000 { 29 device_type = "memory"; 30 reg = <0x0 0x0 0x0 0x80000000>; 31 }; 32 33 simple-bus { 34 compatible = "simple-bus"; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 reg_usb3h0_vbus: usb3-vbus0 { 39 compatible = "regulator-fixed"; 40 pinctrl-names = "default"; 41 pinctrl-0 = <&cpm_xhci_vbus_pins>; 42 regulator-name = "reg-usb3h0-vbus"; 43 regulator-min-microvolt = <5000000>; 44 regulator-max-microvolt = <5000000>; 45 startup-delay-us = <500000>; 46 enable-active-high; 47 regulator-always-on; 48 regulator-boot-on; 49 gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */ 50 }; 51 }; 52}; 53 54/* Accessible over the mini-USB CON9 connector on the main board */ 55&uart0 { 56 status = "okay"; 57}; 58 59&ap_pinctl { 60 /* 61 * MPP Bus: 62 * eMMC [0-10] 63 * UART0 [11,19] 64 */ 65 /* 0 1 2 3 4 5 6 7 8 9 */ 66 pin-func = < 1 1 1 1 1 1 1 1 1 1 67 1 3 0 0 0 0 0 0 0 3 >; 68}; 69 70/* on-board eMMC */ 71&ap_sdhci0 { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&ap_emmc_pins>; 74 bus-width= <8>; 75 status = "okay"; 76}; 77 78&cpm_pinctl { 79 /* 80 * MPP Bus: 81 * [0-31] = 0xff: Keep default CP0_shared_pins: 82 * [11] CLKOUT_MPP_11 (out) 83 * [23] LINK_RD_IN_CP2CP (in) 84 * [25] CLKOUT_MPP_25 (out) 85 * [29] AVS_FB_IN_CP2CP (in) 86 * [32,34] SMI 87 * [33] MSS power down 88 * [35-38] CP0 I2C1 and I2C0 89 * [39] MSS CKE Enable 90 * [40,41] CP0 UART1 TX/RX 91 * [42,43] XSMI (controls two 10G phys) 92 * [47] USB VBUS EN 93 * [48] FAN PWM 94 * [49] 10G port 1 interrupt 95 * [50] 10G port 0 interrupt 96 * [51] 2.5G SFP TX fault 97 * [52] PCIe reset out 98 * [53] 2.5G SFP mode 99 * [54] 2.5G SFP LOS 100 * [55] Micro SD card detect 101 * [56-61] Micro SD 102 * [62] CP1 KR SFP FAULT 103 */ 104 /* 0 1 2 3 4 5 6 7 8 9 */ 105 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 106 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 107 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 108 0xff 0 7 0xa 7 2 2 2 2 0xa 109 7 7 8 8 0 0 0 0 0 0 110 0 0 0 0 0 0 0xe 0xe 0xe 0xe 111 0xe 0xe 0 >; 112 113 cpm_xhci_vbus_pins: cpm-xhci-vbus-pins { 114 marvell,pins = < 47 >; 115 marvell,function = <0>; 116 }; 117 118 cpm_pcie_reset_pins: cpm-pcie-reset-pins { 119 marvell,pins = < 52 >; 120 marvell,function = <0>; 121 }; 122}; 123 124/* uSD slot */ 125&cpm_sdhci0 { 126 pinctrl-names = "default"; 127 pinctrl-0 = <&cpm_sdhci_pins>; 128 bus-width= <4>; 129 status = "okay"; 130}; 131 132/* PCIe x4 */ 133&cpm_pcie0 { 134 num-lanes = <4>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&cpm_pcie_reset_pins>; 137 marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */ 138 status = "okay"; 139}; 140 141&cpm_i2c0 { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&cpm_i2c0_pins>; 144 status = "okay"; 145 clock-frequency = <100000>; 146}; 147 148&cpm_i2c1 { 149 pinctrl-names = "default"; 150 pinctrl-0 = <&cpm_i2c1_pins>; 151 status = "okay"; 152 clock-frequency = <100000>; 153}; 154 155&cpm_sata0 { 156 status = "okay"; 157}; 158 159&cpm_comphy { 160 /* 161 * CP0 Serdes Configuration: 162 * Lane 0: PCIe0 (x4) 163 * Lane 1: PCIe0 (x4) 164 * Lane 2: PCIe0 (x4) 165 * Lane 3: PCIe0 (x4) 166 * Lane 4: KR (10G) 167 * Lane 5: SATA1 168 */ 169 phy0 { 170 phy-type = <PHY_TYPE_PEX0>; 171 }; 172 phy1 { 173 phy-type = <PHY_TYPE_PEX0>; 174 }; 175 phy2 { 176 phy-type = <PHY_TYPE_PEX0>; 177 }; 178 phy3 { 179 phy-type = <PHY_TYPE_PEX0>; 180 }; 181 phy4 { 182 phy-type = <PHY_TYPE_KR>; 183 }; 184 phy5 { 185 phy-type = <PHY_TYPE_SATA1>; 186 }; 187}; 188 189&cps_sata0 { 190 status = "okay"; 191}; 192 193&cps_usb3_0 { 194 vbus-supply = <®_usb3h0_vbus>; 195 status = "okay"; 196}; 197 198&cps_utmi0 { 199 status = "okay"; 200}; 201 202&cps_pinctl { 203 /* 204 * MPP Bus: 205 * [0-5] TDM 206 * [6,7] CP1_UART 0 207 * [8] CP1 10G SFP LOS 208 * [9] CP1 10G PHY RESET 209 * [10] CP1 10G SFP TX Disable 210 * [11] CP1 10G SFP Mode 211 * [12] SPI1 CS1n 212 * [13] SPI1 MISO (TDM and SPI ROM shared) 213 * [14] SPI1 CS0n 214 * [15] SPI1 MOSI (TDM and SPI ROM shared) 215 * [16] SPI1 CLK (TDM and SPI ROM shared) 216 * [24] CP1 2.5G SFP TX Disable 217 * [26] CP0 10G SFP TX Fault 218 * [27] CP0 10G SFP Mode 219 * [28] CP0 10G SFP LOS 220 * [29] CP0 10G SFP TX Disable 221 * [30] USB Over current indication 222 * [31] 10G Port 0 phy reset 223 * [32-62] = 0xff: Keep default CP1_shared_pins: 224 */ 225 /* 0 1 2 3 4 5 6 7 8 9 */ 226 pin-func = < 0x4 0x4 0x4 0x4 0x4 0x4 0x8 0x8 0x0 0x0 227 0x0 0x0 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff 228 0xff 0xff 0xff 0xff 0x0 0xff 0x0 0x0 0x0 0x0 229 0x0 0x0 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 230 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 231 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 232 0xff 0xff 0xff>; 233}; 234 235&cps_spi1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&cps_spi1_pins>; 238 status = "okay"; 239 240 spi-flash@0 { 241 #address-cells = <1>; 242 #size-cells = <1>; 243 compatible = "jedec,spi-nor"; 244 reg = <0>; 245 spi-max-frequency = <10000000>; 246 247 partitions { 248 compatible = "fixed-partitions"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 252 partition@0 { 253 label = "U-Boot"; 254 reg = <0 0x200000>; 255 }; 256 partition@400000 { 257 label = "Filesystem"; 258 reg = <0x200000 0xce0000>; 259 }; 260 }; 261 }; 262}; 263 264&cps_comphy { 265 /* 266 * CP1 Serdes Configuration: 267 * Lane 0: SGMII2 268 * Lane 1: SATA 0 269 * Lane 2: USB HOST 0 270 * Lane 3: SATA1 271 * Lane 4: KR (10G) 272 * Lane 5: SGMII3 273 */ 274 phy0 { 275 phy-type = <PHY_TYPE_SGMII2>; 276 phy-speed = <PHY_SPEED_1_25G>; 277 }; 278 phy1 { 279 phy-type = <PHY_TYPE_SATA0>; 280 }; 281 phy2 { 282 phy-type = <PHY_TYPE_USB3_HOST0>; 283 }; 284 phy3 { 285 phy-type = <PHY_TYPE_SATA1>; 286 }; 287 phy4 { 288 phy-type = <PHY_TYPE_KR>; 289 }; 290 phy5 { 291 phy-type = <PHY_TYPE_SGMII3>; 292 }; 293}; 294