1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada 8040 Development board platform 45 */ 46 47#include "armada-8040.dtsi" 48 49/ { 50 model = "Marvell Armada 8040 DB board"; 51 compatible = "marvell,armada8040-db", "marvell,armada8040", 52 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 53 54 chosen { 55 stdout-path = "serial0:115200n8"; 56 }; 57 58 aliases { 59 i2c0 = &cpm_i2c0; 60 spi0 = &cps_spi1; 61 }; 62 63 memory@00000000 { 64 device_type = "memory"; 65 reg = <0x0 0x0 0x0 0x80000000>; 66 }; 67}; 68 69/* Accessible over the mini-USB CON9 connector on the main board */ 70&uart0 { 71 status = "okay"; 72}; 73 74&ap_pinctl { 75 /* MPP Bus: 76 * SDIO [0-10] 77 * UART0 [11,19] 78 */ 79 /* 0 1 2 3 4 5 6 7 8 9 */ 80 pin-func = < 1 1 1 1 1 1 1 1 1 1 81 1 3 0 0 0 0 0 0 0 3 >; 82}; 83 84&cpm_pinctl { 85 /* MPP Bus: 86 * [0-31] = 0xff: Keep default CP0_shared_pins 87 * [11] CLKOUT_MPP_11 (out) 88 * [23] LINK_RD_IN_CP2CP (in) 89 * [25] CLKOUT_MPP_25 (out) 90 * [29] AVS_FB_IN_CP2CP (in) 91 * [32,34] GE_MDIO/MDC 92 * [33] GPIO: GE_INT#/push button/Wake 93 * [35] MSS_GPIO[3]: MSS_PWDN 94 * [36] MSS_GPIO[5]: MSS_VTT_EN 95 * [37-38] I2C0 96 * [39] PTP_CLK 97 * [40-41] SATA[0/1]_PRESENT_ACTIVEn 98 * [42-43] XG_MDC/XG_MDIO (XSMI) 99 * [44-55] RGMII1 100 * [56-62] SD 101 */ 102 /* 0 1 2 3 4 5 6 7 8 9 */ 103 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 104 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 105 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 106 0xff 0xff 0x7 0x0 0x7 0xa 0xa 0x2 0x2 0x5 107 0x9 0x9 0x8 0x8 0x1 0x1 0x1 0x1 0x1 0x1 108 0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe 109 0xe 0xe 0xe>; 110}; 111 112&cpm_comphy { 113 /* Serdes Configuration: 114 * Lane 0: PCIe0 (x1) 115 * Lane 1: SATA0 116 * Lane 2: SFI (10G) 117 * Lane 3: SATA1 118 * Lane 4: USB3_HOST1 119 * Lane 5: PCIe2 (x1) 120 */ 121 phy0 { 122 phy-type = <PHY_TYPE_PEX0>; 123 }; 124 phy1 { 125 phy-type = <PHY_TYPE_SATA0>; 126 }; 127 phy2 { 128 phy-type = <PHY_TYPE_SFI>; 129 }; 130 phy3 { 131 phy-type = <PHY_TYPE_SATA1>; 132 }; 133 phy4 { 134 phy-type = <PHY_TYPE_USB3_HOST1>; 135 }; 136 phy5 { 137 phy-type = <PHY_TYPE_PEX2>; 138 }; 139}; 140 141/* CON6 on CP0 expansion */ 142&cpm_pcie0 { 143 status = "okay"; 144}; 145 146&cpm_pcie1 { 147 status = "disabled"; 148}; 149 150/* CON5 on CP0 expansion */ 151&cpm_pcie2 { 152 status = "okay"; 153}; 154 155&cpm_i2c0 { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&cpm_i2c0_pins>; 158 status = "okay"; 159 clock-frequency = <100000>; 160}; 161 162/* CON4 on CP0 expansion */ 163&cpm_sata0 { 164 status = "okay"; 165}; 166 167/* CON9 on CP0 expansion */ 168&cpm_usb3_0 { 169 status = "okay"; 170}; 171 172/* CON10 on CP0 expansion */ 173&cpm_usb3_1 { 174 status = "okay"; 175}; 176 177&cpm_utmi0 { 178 status = "okay"; 179}; 180 181&cpm_utmi1 { 182 status = "okay"; 183}; 184 185&cps_pinctl { 186 /* MPP Bus: 187 * [0-11] RGMII0 188 * [13-16] SPI1 189 * [27,31] GE_MDIO/MDC 190 * [28] SATA1_PRESENT_ACTIVEn 191 * [29-30] UART0 192 * [32-62] = 0xff: Keep default CP1_shared_pins 193 */ 194 /* 0 1 2 3 4 5 6 7 8 9 */ 195 pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 196 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0xff 0xff 0xff 197 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0x9 0xa 198 0xA 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 199 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 200 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 201 0xff 0xff 0xff>; 202}; 203 204&cps_comphy { 205 /* Serdes Configuration: 206 * Lane 0: PCIe0 (x1) 207 * Lane 1: SATA0 208 * Lane 2: SFI (10G) 209 * Lane 3: SATA1 210 * Lane 4: PCIe1 (x1) 211 * Lane 5: PCIe2 (x1) 212 */ 213 phy0 { 214 phy-type = <PHY_TYPE_PEX0>; 215 }; 216 phy1 { 217 phy-type = <PHY_TYPE_SATA0>; 218 }; 219 phy2 { 220 phy-type = <PHY_TYPE_SFI>; 221 }; 222 phy3 { 223 phy-type = <PHY_TYPE_SATA1>; 224 }; 225 phy4 { 226 phy-type = <PHY_TYPE_PEX1>; 227 }; 228 phy5 { 229 phy-type = <PHY_TYPE_PEX2>; 230 }; 231}; 232 233/* CON6 on CP1 expansion */ 234&cps_pcie0 { 235 status = "okay"; 236}; 237 238&cps_pcie1 { 239 status = "okay"; 240}; 241 242/* CON5 on CP1 expansion */ 243&cps_pcie2 { 244 status = "okay"; 245}; 246 247&cps_spi1 { 248 pinctrl-names = "default"; 249 pinctrl-0 = <&cps_spi1_pins>; 250 status = "okay"; 251 252 spi-flash@0 { 253 #address-cells = <1>; 254 #size-cells = <1>; 255 compatible = "jedec,spi-nor"; 256 reg = <0>; 257 spi-max-frequency = <10000000>; 258 259 partitions { 260 compatible = "fixed-partitions"; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 264 partition@0 { 265 label = "U-Boot"; 266 reg = <0 0x200000>; 267 }; 268 partition@400000 { 269 label = "Filesystem"; 270 reg = <0x200000 0xce0000>; 271 }; 272 }; 273 }; 274}; 275 276/* CON4 on CP1 expansion */ 277&cps_sata0 { 278 status = "okay"; 279}; 280 281/* CON9 on CP1 expansion */ 282&cps_usb3_0 { 283 status = "okay"; 284}; 285 286/* CON10 on CP1 expansion */ 287&cps_usb3_1 { 288 status = "okay"; 289}; 290 291&cps_utmi0 { 292 status = "okay"; 293}; 294 295&cpm_mdio { 296 phy1: ethernet-phy@1 { 297 reg = <1>; 298 }; 299}; 300 301&cpm_ethernet { 302 status = "okay"; 303}; 304 305&cpm_eth2 { 306 status = "okay"; 307 phy = <&phy1>; 308 phy-mode = "rgmii-id"; 309}; 310