1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada 8040 Development board platform 45 */ 46 47#include "armada-8040.dtsi" 48 49/ { 50 model = "Marvell Armada 8040 DB board"; 51 compatible = "marvell,armada8040-db", "marvell,armada8040", 52 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 53 54 chosen { 55 stdout-path = "serial0:115200n8"; 56 }; 57 58 aliases { 59 i2c0 = &cpm_i2c0; 60 spi0 = &cps_spi1; 61 }; 62 63 memory@00000000 { 64 device_type = "memory"; 65 reg = <0x0 0x0 0x0 0x80000000>; 66 }; 67}; 68 69/* Accessible over the mini-USB CON9 connector on the main board */ 70&uart0 { 71 status = "okay"; 72}; 73 74&ap_pinctl { 75 /* MPP Bus: 76 * SDIO [0-10] 77 * UART0 [11,19] 78 */ 79 /* 0 1 2 3 4 5 6 7 8 9 */ 80 pin-func = < 1 1 1 1 1 1 1 1 1 1 81 1 3 0 0 0 0 0 0 0 3 >; 82}; 83 84&cpm_pinctl { 85 /* MPP Bus: 86 * [0-31] = 0xff: Keep default CP0_shared_pins: 87 * [11] CLKOUT_MPP_11 (out) 88 * [23] LINK_RD_IN_CP2CP (in) 89 * [25] CLKOUT_MPP_25 (out) 90 * [29] AVS_FB_IN_CP2CP (in) 91 * [32,34] SMI 92 * [31] GPIO: push button/Wake 93 * [35-36] GPIO 94 * [37-38] I2C 95 * [40-41] SATA[0/1]_PRESENT_ACTIVEn 96 * [42-43] XSMI 97 * [44-55] RGMII1 98 * [56-62] SD 99 */ 100 /* 0 1 2 3 4 5 6 7 8 9 */ 101 pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 102 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 103 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 104 0xff 0 7 0 7 0 0 2 2 0 105 0 0 8 8 1 1 1 1 1 1 106 1 1 1 1 1 1 0xe 0xe 0xe 0xe 107 0xe 0xe 0xe >; 108}; 109 110/* CON5 on CP0 expansion */ 111&cpm_pcie2 { 112 status = "okay"; 113}; 114 115&cpm_i2c0 { 116 pinctrl-names = "default"; 117 pinctrl-0 = <&cpm_i2c0_pins>; 118 status = "okay"; 119 clock-frequency = <100000>; 120}; 121 122/* CON4 on CP0 expansion */ 123&cpm_sata0 { 124 status = "okay"; 125}; 126 127/* CON9 on CP0 expansion */ 128&cpm_usb3_0 { 129 status = "okay"; 130}; 131 132/* CON10 on CP0 expansion */ 133&cpm_usb3_1 { 134 status = "okay"; 135}; 136 137&cps_pinctl { 138 /* MPP Bus: 139 * [0-11] RGMII0 140 * [13-16] SPI1 141 * [27,31] GE_MDIO/MDC 142 * [32-62] = 0xff: Keep default CP1_shared_pins: 143 */ 144 /* 0 1 2 3 4 5 6 7 8 9 */ 145 pin-func = < 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 146 0x3 0x3 0xff 0x3 0x3 0x3 0x3 0xff 0xff 0xff 147 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8 0xff 0xff 148 0xff 0x8 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 149 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 150 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 151 0xff 0xff 0xff >; 152}; 153 154/* CON5 on CP1 expansion */ 155&cps_pcie2 { 156 status = "okay"; 157}; 158 159&cps_spi1 { 160 pinctrl-names = "default"; 161 pinctrl-0 = <&cps_spi1_pins>; 162 status = "okay"; 163 164 spi-flash@0 { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 compatible = "jedec,spi-nor"; 168 reg = <0>; 169 spi-max-frequency = <10000000>; 170 171 partitions { 172 compatible = "fixed-partitions"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 176 partition@0 { 177 label = "U-Boot"; 178 reg = <0 0x200000>; 179 }; 180 partition@400000 { 181 label = "Filesystem"; 182 reg = <0x200000 0xce0000>; 183 }; 184 }; 185 }; 186}; 187 188/* CON4 on CP1 expansion */ 189&cps_sata0 { 190 status = "okay"; 191}; 192 193/* CON9 on CP1 expansion */ 194&cps_usb3_0 { 195 status = "okay"; 196}; 197 198/* CON10 on CP1 expansion */ 199&cps_usb3_1 { 200 status = "okay"; 201}; 202 203&cpm_comphy { 204 /* 205 * Serdes Configuration: 206 * Lane 0: SGMII2 207 * Lane 1: USB3_HOST0 208 * Lane 2: KR (10G) 209 * Lane 3: SATA1 210 * Lane 4: USB3_HOST1 211 * Lane 5: PEX2x1 212 */ 213 phy0 { 214 phy-type = <PHY_TYPE_SGMII2>; 215 phy-speed = <PHY_SPEED_3_125G>; 216 }; 217 218 phy1 { 219 phy-type = <PHY_TYPE_USB3_HOST0>; 220 }; 221 222 phy2 { 223 phy-type = <PHY_TYPE_KR>; 224 }; 225 226 phy3 { 227 phy-type = <PHY_TYPE_SATA1>; 228 }; 229 230 phy4 { 231 phy-type = <PHY_TYPE_USB3_HOST1>; 232 }; 233 234 phy5 { 235 phy-type = <PHY_TYPE_PEX2>; 236 }; 237}; 238 239&cps_comphy { 240 /* 241 * Serdes Configuration: 242 * Lane 0: SGMII2 243 * Lane 1: USB3_HOST0 244 * Lane 2: KR (10G) 245 * Lane 3: SATA1 246 * Lane 4: Unconnected 247 * Lane 5: PEX2x1 248 */ 249 phy0 { 250 phy-type = <PHY_TYPE_SGMII2>; 251 phy-speed = <PHY_SPEED_3_125G>; 252 }; 253 254 phy1 { 255 phy-type = <PHY_TYPE_USB3_HOST0>; 256 }; 257 258 phy2 { 259 phy-type = <PHY_TYPE_KR>; 260 }; 261 262 phy3 { 263 phy-type = <PHY_TYPE_SATA1>; 264 }; 265 266 phy4 { 267 phy-type = <PHY_TYPE_UNCONNECTED>; 268 }; 269 270 phy5 { 271 phy-type = <PHY_TYPE_PEX2>; 272 }; 273}; 274 275&cpm_utmi0 { 276 status = "okay"; 277}; 278 279&cpm_utmi1 { 280 status = "okay"; 281}; 282 283&cps_utmi0 { 284 status = "okay"; 285}; 286