xref: /openbmc/u-boot/arch/arm/dts/armada-8040-db.dts (revision 87a62bce)
1/*
2 * Copyright (C) 2016 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This library is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This library is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for Marvell Armada 8040 Development board platform
45 */
46
47#include "armada-8040.dtsi"
48
49/ {
50	model = "Marvell Armada 8040 DB board";
51	compatible = "marvell,armada8040-db", "marvell,armada8040",
52		     "marvell,armada-ap806-quad", "marvell,armada-ap806";
53
54	chosen {
55		stdout-path = "serial0:115200n8";
56	};
57
58	aliases {
59		i2c0 = &cpm_i2c0;
60		spi0 = &cps_spi1;
61	};
62
63	memory@00000000 {
64		device_type = "memory";
65		reg = <0x0 0x0 0x0 0x80000000>;
66	};
67};
68
69/* Accessible over the mini-USB CON9 connector on the main board */
70&uart0 {
71	status = "okay";
72};
73
74&ap_pinctl {
75	/* MPP Bus:
76	 * SDIO  [0-10]
77	 * UART0 [11,19]
78	 */
79		  /* 0 1 2 3 4 5 6 7 8 9 */
80	pin-func = < 1 1 1 1 1 1 1 1 1 1
81		     1 3 0 0 0 0 0 0 0 3 >;
82};
83
84&ap_sdhci0 {
85	pinctrl-names = "default";
86	pinctrl-0 = <&ap_emmc_pins>;
87	bus-width = <8>;
88	status = "okay";
89};
90
91&cpm_pinctl {
92	/* MPP Bus:
93	 *	[0-31]	= 0xff: Keep default CP0_shared_pins
94	 *	[11]	CLKOUT_MPP_11 (out)
95	 *	[23]	LINK_RD_IN_CP2CP (in)
96	 *	[25]	CLKOUT_MPP_25 (out)
97	 *	[29]	AVS_FB_IN_CP2CP (in)
98	 *	[32,34]	GE_MDIO/MDC
99	 *	[33]	GPIO: GE_INT#/push button/Wake
100	 *	[35]	MSS_GPIO[3]: MSS_PWDN
101	 *	[36]	MSS_GPIO[5]: MSS_VTT_EN
102	 *	[37-38]	I2C0
103	 *	[39]	PTP_CLK
104	 *	[40-41]	SATA[0/1]_PRESENT_ACTIVEn
105	 *	[42-43]	XG_MDC/XG_MDIO (XSMI)
106	 *	[44-55]	RGMII1
107	 *	[56-62]	SD
108	 */
109	/*   0    1    2    3    4    5    6    7    8    9 */
110	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
111		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
112		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
113		     0xff 0xff 0x7  0x0  0x7  0xa  0xa  0x2  0x2  0x5
114		     0x9  0x9  0x8  0x8  0x1  0x1  0x1  0x1  0x1  0x1
115		     0x1  0x1  0x1  0x1  0x1  0x1  0xe  0xe  0xe  0xe
116		     0xe  0xe  0xe>;
117};
118
119&cpm_comphy {
120	/* Serdes Configuration:
121	 *	Lane 0: PCIe0 (x1)
122	 *	Lane 1: SATA0
123	 *	Lane 2: SFI (10G)
124	 *	Lane 3: SATA1
125	 *	Lane 4: USB3_HOST1
126	 *	Lane 5: PCIe2 (x1)
127	 */
128	phy0 {
129		phy-type = <PHY_TYPE_PEX0>;
130	};
131	phy1 {
132		phy-type = <PHY_TYPE_SATA0>;
133	};
134	phy2 {
135		phy-type = <PHY_TYPE_SFI>;
136	};
137	phy3 {
138		phy-type = <PHY_TYPE_SATA1>;
139	};
140	phy4 {
141		phy-type = <PHY_TYPE_USB3_HOST1>;
142	};
143	phy5 {
144		phy-type = <PHY_TYPE_PEX2>;
145	};
146};
147
148/* CON6 on CP0 expansion */
149&cpm_pcie0 {
150	status = "okay";
151};
152
153&cpm_pcie1 {
154	status = "disabled";
155};
156
157/* CON5 on CP0 expansion */
158&cpm_pcie2 {
159	status = "okay";
160};
161
162&cpm_i2c0 {
163	pinctrl-names = "default";
164	pinctrl-0 = <&cpm_i2c0_pins>;
165	status = "okay";
166	clock-frequency = <100000>;
167};
168
169/* CON4 on CP0 expansion */
170&cpm_sata0 {
171	status = "okay";
172};
173
174/* CON9 on CP0 expansion */
175&cpm_usb3_0 {
176	status = "okay";
177};
178
179/* CON10 on CP0 expansion */
180&cpm_usb3_1 {
181	status = "okay";
182};
183
184&cpm_utmi0 {
185	status = "okay";
186};
187
188&cpm_utmi1 {
189	status = "okay";
190};
191
192&cpm_sdhci0 {
193	pinctrl-names = "default";
194	pinctrl-0 = <&cpm_sdhci_pins>;
195	bus-width = <4>;
196	status = "okay";
197};
198
199&cps_pinctl {
200	/* MPP Bus:
201	 *	[0-11]	RGMII0
202	 *	[13-16]	SPI1
203	 *	[27,31]	GE_MDIO/MDC
204	 *	[28]	SATA1_PRESENT_ACTIVEn
205	 *	[29-30]	UART0
206	 *	[32-62]	= 0xff: Keep default CP1_shared_pins
207	 */
208	/*   0    1    2    3    4    5    6    7    8    9 */
209	pin-func = < 0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3  0x3
210		     0x3  0x3  0x3  0x3  0x3  0x3  0x3  0xff 0xff 0xff
211		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x8  0x9  0xa
212		     0xA  0x8  0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
213		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
214		     0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
215		     0xff 0xff 0xff>;
216};
217
218&cps_comphy {
219	/* Serdes Configuration:
220	 *	Lane 0: PCIe0 (x1)
221	 *	Lane 1: SATA0
222	 *	Lane 2: SFI (10G)
223	 *	Lane 3: SATA1
224	 *	Lane 4: PCIe1 (x1)
225	 *	Lane 5: PCIe2 (x1)
226	 */
227	phy0 {
228		phy-type = <PHY_TYPE_PEX0>;
229	};
230	phy1 {
231		phy-type = <PHY_TYPE_SATA0>;
232	};
233	phy2 {
234		phy-type = <PHY_TYPE_SFI>;
235	};
236	phy3 {
237		phy-type = <PHY_TYPE_SATA1>;
238	};
239	phy4 {
240		phy-type = <PHY_TYPE_PEX1>;
241	};
242	phy5 {
243		phy-type = <PHY_TYPE_PEX2>;
244	};
245};
246
247/* CON6 on CP1 expansion */
248&cps_pcie0 {
249	status = "okay";
250};
251
252&cps_pcie1 {
253	status = "okay";
254};
255
256/* CON5 on CP1 expansion */
257&cps_pcie2 {
258	status = "okay";
259};
260
261&cps_spi1 {
262	pinctrl-names = "default";
263	pinctrl-0 = <&cps_spi1_pins>;
264	status = "okay";
265
266	spi-flash@0 {
267		#address-cells = <1>;
268		#size-cells = <1>;
269		compatible = "jedec,spi-nor";
270		reg = <0>;
271		spi-max-frequency = <10000000>;
272
273		partitions {
274			compatible = "fixed-partitions";
275			#address-cells = <1>;
276			#size-cells = <1>;
277
278			partition@0 {
279				label = "U-Boot";
280				reg = <0 0x200000>;
281			};
282			partition@400000 {
283				label = "Filesystem";
284				reg = <0x200000 0xce0000>;
285			};
286		};
287	};
288};
289
290/* CON4 on CP1 expansion */
291&cps_sata0 {
292	status = "okay";
293};
294
295/* CON9 on CP1 expansion */
296&cps_usb3_0 {
297	status = "okay";
298};
299
300/* CON10 on CP1 expansion */
301&cps_usb3_1 {
302	status = "okay";
303};
304
305&cps_utmi0 {
306	status = "okay";
307};
308
309&cpm_mdio {
310	phy1: ethernet-phy@1 {
311		reg = <1>;
312	};
313};
314
315&cpm_ethernet {
316	status = "okay";
317};
318
319&cpm_eth2 {
320	status = "okay";
321	phy = <&phy1>;
322	phy-mode = "rgmii-id";
323};
324