xref: /openbmc/u-boot/arch/arm/dts/armada-38x.dtsi (revision 5df93c55)
1/*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 *  a) This file is free software; you can redistribute it and/or
16 *     modify it under the terms of the GNU General Public License as
17 *     published by the Free Software Foundation; either version 2 of the
18 *     License, or (at your option) any later version.
19 *
20 *     This file is distributed in the hope that it will be useful
21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 *     GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49#include "skeleton.dtsi"
50#include <dt-bindings/interrupt-controller/arm-gic.h>
51#include <dt-bindings/interrupt-controller/irq.h>
52
53#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54
55/ {
56	model = "Marvell Armada 38x family SoC";
57	compatible = "marvell,armada380";
58
59	aliases {
60		gpio0 = &gpio0;
61		gpio1 = &gpio1;
62		serial0 = &uart0;
63		serial1 = &uart1;
64	};
65
66	pmu {
67		compatible = "arm,cortex-a9-pmu";
68		interrupts-extended = <&mpic 3>;
69	};
70
71	soc {
72		compatible = "marvell,armada380-mbus", "simple-bus";
73		#address-cells = <2>;
74		#size-cells = <1>;
75		controller = <&mbusc>;
76		interrupt-parent = <&gic>;
77		pcie-mem-aperture = <0xe0000000 0x8000000>;
78		pcie-io-aperture  = <0xe8000000 0x100000>;
79
80		bootrom {
81			compatible = "marvell,bootrom";
82			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
83		};
84
85		devbus-bootcs {
86			compatible = "marvell,mvebu-devbus";
87			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
88			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
89			#address-cells = <1>;
90			#size-cells = <1>;
91			clocks = <&coreclk 0>;
92			status = "disabled";
93		};
94
95		devbus-cs0 {
96			compatible = "marvell,mvebu-devbus";
97			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
98			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
99			#address-cells = <1>;
100			#size-cells = <1>;
101			clocks = <&coreclk 0>;
102			status = "disabled";
103		};
104
105		devbus-cs1 {
106			compatible = "marvell,mvebu-devbus";
107			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
108			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109			#address-cells = <1>;
110			#size-cells = <1>;
111			clocks = <&coreclk 0>;
112			status = "disabled";
113		};
114
115		devbus-cs2 {
116			compatible = "marvell,mvebu-devbus";
117			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
118			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119			#address-cells = <1>;
120			#size-cells = <1>;
121			clocks = <&coreclk 0>;
122			status = "disabled";
123		};
124
125		devbus-cs3 {
126			compatible = "marvell,mvebu-devbus";
127			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
128			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129			#address-cells = <1>;
130			#size-cells = <1>;
131			clocks = <&coreclk 0>;
132			status = "disabled";
133		};
134
135		internal-regs {
136			compatible = "simple-bus";
137			#address-cells = <1>;
138			#size-cells = <1>;
139			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
140
141			L2: cache-controller@8000 {
142				compatible = "arm,pl310-cache";
143				reg = <0x8000 0x1000>;
144				cache-unified;
145				cache-level = <2>;
146			};
147
148			scu@c000 {
149				compatible = "arm,cortex-a9-scu";
150				reg = <0xc000 0x58>;
151			};
152
153			timer@c600 {
154				compatible = "arm,cortex-a9-twd-timer";
155				reg = <0xc600 0x20>;
156				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
157				clocks = <&coreclk 2>;
158			};
159
160			gic: interrupt-controller@d000 {
161				compatible = "arm,cortex-a9-gic";
162				#interrupt-cells = <3>;
163				#size-cells = <0>;
164				interrupt-controller;
165				reg = <0xd000 0x1000>,
166				      <0xc100 0x100>;
167			};
168
169			spi0: spi@10600 {
170				compatible = "marvell,armada-380-spi",
171						"marvell,orion-spi";
172				reg = <0x10600 0x50>;
173				#address-cells = <1>;
174				#size-cells = <0>;
175				cell-index = <0>;
176				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
177				clocks = <&coreclk 0>;
178				status = "disabled";
179			};
180
181			spi1: spi@10680 {
182				compatible = "marvell,armada-380-spi",
183						"marvell,orion-spi";
184				reg = <0x10680 0x50>;
185				#address-cells = <1>;
186				#size-cells = <0>;
187				cell-index = <1>;
188				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
189				clocks = <&coreclk 0>;
190				status = "disabled";
191			};
192
193			i2c0: i2c@11000 {
194				compatible = "marvell,mv64xxx-i2c";
195				reg = <0x11000 0x20>;
196				#address-cells = <1>;
197				#size-cells = <0>;
198				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
199				timeout-ms = <1000>;
200				clocks = <&coreclk 0>;
201				status = "disabled";
202			};
203
204			i2c1: i2c@11100 {
205				compatible = "marvell,mv64xxx-i2c";
206				reg = <0x11100 0x20>;
207				#address-cells = <1>;
208				#size-cells = <0>;
209				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
210				timeout-ms = <1000>;
211				clocks = <&coreclk 0>;
212				status = "disabled";
213			};
214
215			uart0: serial@12000 {
216				compatible = "snps,dw-apb-uart";
217				reg = <0x12000 0x100>;
218				reg-shift = <2>;
219				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
220				reg-io-width = <1>;
221				clocks = <&coreclk 0>;
222				status = "disabled";
223			};
224
225			uart1: serial@12100 {
226				compatible = "snps,dw-apb-uart";
227				reg = <0x12100 0x100>;
228				reg-shift = <2>;
229				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
230				reg-io-width = <1>;
231				clocks = <&coreclk 0>;
232				status = "disabled";
233			};
234
235			pinctrl: pinctrl@18000 {
236				reg = <0x18000 0x20>;
237
238				ge0_rgmii_pins: ge-rgmii-pins-0 {
239					marvell,pins = "mpp6", "mpp7", "mpp8",
240						       "mpp9", "mpp10", "mpp11",
241						       "mpp12", "mpp13", "mpp14",
242						       "mpp15", "mpp16", "mpp17";
243					marvell,function = "ge0";
244				};
245
246				ge1_rgmii_pins: ge-rgmii-pins-1 {
247					marvell,pins = "mpp21", "mpp27", "mpp28",
248						       "mpp29", "mpp30", "mpp31",
249						       "mpp32", "mpp37", "mpp38",
250						       "mpp39", "mpp40", "mpp41";
251					marvell,function = "ge1";
252				};
253
254				i2c0_pins: i2c-pins-0 {
255					marvell,pins = "mpp2", "mpp3";
256					marvell,function = "i2c0";
257				};
258
259				mdio_pins: mdio-pins {
260					marvell,pins = "mpp4", "mpp5";
261					marvell,function = "ge";
262				};
263
264				ref_clk0_pins: ref-clk-pins-0 {
265					marvell,pins = "mpp45";
266					marvell,function = "ref";
267				};
268
269				ref_clk1_pins: ref-clk-pins-1 {
270					marvell,pins = "mpp46";
271					marvell,function = "ref";
272				};
273
274				spi0_pins: spi-pins-0 {
275					marvell,pins = "mpp22", "mpp23", "mpp24",
276						       "mpp25";
277					marvell,function = "spi0";
278				};
279
280				spi1_pins: spi-pins-1 {
281					marvell,pins = "mpp56", "mpp57", "mpp58",
282						       "mpp59";
283					marvell,function = "spi1";
284				};
285
286				uart0_pins: uart-pins-0 {
287					marvell,pins = "mpp0", "mpp1";
288					marvell,function = "ua0";
289				};
290
291				uart1_pins: uart-pins-1 {
292					marvell,pins = "mpp19", "mpp20";
293					marvell,function = "ua1";
294				};
295
296				sdhci_pins: sdhci-pins {
297					marvell,pins = "mpp48", "mpp49", "mpp50",
298						       "mpp52", "mpp53", "mpp54",
299						       "mpp55", "mpp57", "mpp58",
300						       "mpp59";
301					marvell,function = "sd0";
302				};
303
304				sata0_pins: sata-pins-0 {
305					marvell,pins = "mpp20";
306					marvell,function = "sata0";
307				};
308
309				sata1_pins: sata-pins-1 {
310					marvell,pins = "mpp19";
311					marvell,function = "sata1";
312				};
313
314				sata2_pins: sata-pins-2 {
315					marvell,pins = "mpp47";
316					marvell,function = "sata2";
317				};
318
319				sata3_pins: sata-pins-3 {
320					marvell,pins = "mpp44";
321					marvell,function = "sata3";
322				};
323			};
324
325			gpio0: gpio@18100 {
326				compatible = "marvell,orion-gpio";
327				reg = <0x18100 0x40>;
328				ngpios = <32>;
329				gpio-controller;
330				#gpio-cells = <2>;
331				interrupt-controller;
332				#interrupt-cells = <2>;
333				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
334					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
335					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
336					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
337			};
338
339			gpio1: gpio@18140 {
340				compatible = "marvell,orion-gpio";
341				reg = <0x18140 0x40>;
342				ngpios = <28>;
343				gpio-controller;
344				#gpio-cells = <2>;
345				interrupt-controller;
346				#interrupt-cells = <2>;
347				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
348					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
349					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
350					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
351			};
352
353			system-controller@18200 {
354				compatible = "marvell,armada-380-system-controller",
355					     "marvell,armada-370-xp-system-controller";
356				reg = <0x18200 0x100>;
357			};
358
359			gateclk: clock-gating-control@18220 {
360				compatible = "marvell,armada-380-gating-clock";
361				reg = <0x18220 0x4>;
362				clocks = <&coreclk 0>;
363				#clock-cells = <1>;
364			};
365
366			coreclk: mvebu-sar@18600 {
367				compatible = "marvell,armada-380-core-clock";
368				reg = <0x18600 0x04>;
369				#clock-cells = <1>;
370			};
371
372			mbusc: mbus-controller@20000 {
373				compatible = "marvell,mbus-controller";
374				reg = <0x20000 0x100>, <0x20180 0x20>;
375			};
376
377			mpic: interrupt-controller@20a00 {
378				compatible = "marvell,mpic";
379				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
380				#interrupt-cells = <1>;
381				#size-cells = <1>;
382				interrupt-controller;
383				msi-controller;
384				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
385			};
386
387			timer@20300 {
388				compatible = "marvell,armada-380-timer",
389					     "marvell,armada-xp-timer";
390				reg = <0x20300 0x30>, <0x21040 0x30>;
391				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
392						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
393						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
394						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
395						      <&mpic 5>,
396						      <&mpic 6>;
397				clocks = <&coreclk 2>, <&refclk>;
398				clock-names = "nbclk", "fixed";
399			};
400
401			watchdog@20300 {
402				compatible = "marvell,armada-380-wdt";
403				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
404				clocks = <&coreclk 2>, <&refclk>;
405				clock-names = "nbclk", "fixed";
406			};
407
408			cpurst@20800 {
409				compatible = "marvell,armada-370-cpu-reset";
410				reg = <0x20800 0x10>;
411			};
412
413			mpcore-soc-ctrl@20d20 {
414				compatible = "marvell,armada-380-mpcore-soc-ctrl";
415				reg = <0x20d20 0x6c>;
416			};
417
418			coherency-fabric@21010 {
419				compatible = "marvell,armada-380-coherency-fabric";
420				reg = <0x21010 0x1c>;
421			};
422
423			pmsu@22000 {
424				compatible = "marvell,armada-380-pmsu";
425				reg = <0x22000 0x1000>;
426			};
427
428			eth1: ethernet@30000 {
429				compatible = "marvell,armada-370-neta";
430				reg = <0x30000 0x4000>;
431				interrupts-extended = <&mpic 10>;
432				clocks = <&gateclk 3>;
433				status = "disabled";
434			};
435
436			eth2: ethernet@34000 {
437				compatible = "marvell,armada-370-neta";
438				reg = <0x34000 0x4000>;
439				interrupts-extended = <&mpic 12>;
440				clocks = <&gateclk 2>;
441				status = "disabled";
442			};
443
444			usb@58000 {
445				compatible = "marvell,orion-ehci";
446				reg = <0x58000 0x500>;
447				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
448				clocks = <&gateclk 18>;
449				status = "disabled";
450			};
451
452			xor@60800 {
453				compatible = "marvell,orion-xor";
454				reg = <0x60800 0x100
455				       0x60a00 0x100>;
456				clocks = <&gateclk 22>;
457				status = "okay";
458
459				xor00 {
460					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
461					dmacap,memcpy;
462					dmacap,xor;
463				};
464				xor01 {
465					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
466					dmacap,memcpy;
467					dmacap,xor;
468					dmacap,memset;
469				};
470			};
471
472			xor@60900 {
473				compatible = "marvell,orion-xor";
474				reg = <0x60900 0x100
475				       0x60b00 0x100>;
476				clocks = <&gateclk 28>;
477				status = "okay";
478
479				xor10 {
480					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
481					dmacap,memcpy;
482					dmacap,xor;
483				};
484				xor11 {
485					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
486					dmacap,memcpy;
487					dmacap,xor;
488					dmacap,memset;
489				};
490			};
491
492			eth0: ethernet@70000 {
493				compatible = "marvell,armada-370-neta";
494				reg = <0x70000 0x4000>;
495				interrupts-extended = <&mpic 8>;
496				clocks = <&gateclk 4>;
497				status = "disabled";
498			};
499
500			mdio: mdio@72004 {
501				#address-cells = <1>;
502				#size-cells = <0>;
503				compatible = "marvell,orion-mdio";
504				reg = <0x72004 0x4>;
505				clocks = <&gateclk 4>;
506			};
507
508			rtc@a3800 {
509				compatible = "marvell,armada-380-rtc";
510				reg = <0xa3800 0x20>, <0x184a0 0x0c>;
511				reg-names = "rtc", "rtc-soc";
512				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
513			};
514
515			sata@a8000 {
516				compatible = "marvell,armada-380-ahci";
517				reg = <0xa8000 0x2000>;
518				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
519				clocks = <&gateclk 15>;
520				status = "disabled";
521			};
522
523			sata@e0000 {
524				compatible = "marvell,armada-380-ahci";
525				reg = <0xe0000 0x2000>;
526				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
527				clocks = <&gateclk 30>;
528				status = "disabled";
529			};
530
531			coredivclk: clock@e4250 {
532				compatible = "marvell,armada-380-corediv-clock";
533				reg = <0xe4250 0xc>;
534				#clock-cells = <1>;
535				clocks = <&mainpll>;
536				clock-output-names = "nand";
537			};
538
539			thermal@e8078 {
540				compatible = "marvell,armada380-thermal";
541				reg = <0xe4078 0x4>, <0xe4074 0x4>;
542				status = "okay";
543			};
544
545			flash@d0000 {
546				compatible = "marvell,armada370-nand";
547				reg = <0xd0000 0x54>;
548				#address-cells = <1>;
549				#size-cells = <1>;
550				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
551				clocks = <&coredivclk 0>;
552				status = "disabled";
553			};
554
555			sdhci@d8000 {
556				compatible = "marvell,armada-380-sdhci";
557				reg-names = "sdhci", "mbus", "conf-sdio3";
558				reg = <0xd8000 0x1000>,
559					<0xdc000 0x100>,
560					<0x18454 0x4>;
561				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
562				clocks = <&gateclk 17>;
563				mrvl,clk-delay-cycles = <0x1F>;
564				status = "disabled";
565			};
566
567			usb3@f0000 {
568				compatible = "marvell,armada-380-xhci";
569				reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
570				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
571				clocks = <&gateclk 9>;
572				status = "disabled";
573			};
574
575			usb3@f8000 {
576				compatible = "marvell,armada-380-xhci";
577				reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
578				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
579				clocks = <&gateclk 10>;
580				status = "disabled";
581			};
582		};
583	};
584
585	clocks {
586		/* 2 GHz fixed main PLL */
587		mainpll: mainpll {
588			compatible = "fixed-clock";
589			#clock-cells = <0>;
590			clock-frequency = <1000000000>;
591		};
592
593		/* 25 MHz reference crystal */
594		refclk: oscillator {
595			compatible = "fixed-clock";
596			#clock-cells = <0>;
597			clock-frequency = <25000000>;
598		};
599	};
600};
601