1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 38x family of SoCs. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 */ 11 12#include "skeleton.dtsi" 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15 16#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 17 18/ { 19 model = "Marvell Armada 38x family SoC"; 20 compatible = "marvell,armada380"; 21 22 aliases { 23 gpio0 = &gpio0; 24 gpio1 = &gpio1; 25 serial0 = &uart0; 26 serial1 = &uart1; 27 }; 28 29 pmu { 30 compatible = "arm,cortex-a9-pmu"; 31 interrupts-extended = <&mpic 3>; 32 }; 33 34 soc { 35 compatible = "marvell,armada380-mbus", "simple-bus"; 36 u-boot,dm-pre-reloc; 37 #address-cells = <2>; 38 #size-cells = <1>; 39 controller = <&mbusc>; 40 interrupt-parent = <&gic>; 41 pcie-mem-aperture = <0xe0000000 0x8000000>; 42 pcie-io-aperture = <0xe8000000 0x100000>; 43 44 bootrom { 45 compatible = "marvell,bootrom"; 46 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 47 }; 48 49 devbus_bootcs: devbus-bootcs { 50 compatible = "marvell,mvebu-devbus"; 51 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 52 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 clocks = <&coreclk 0>; 56 status = "disabled"; 57 }; 58 59 devbus_cs0: devbus-cs0 { 60 compatible = "marvell,mvebu-devbus"; 61 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 62 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 clocks = <&coreclk 0>; 66 status = "disabled"; 67 }; 68 69 devbus_cs1: devbus-cs1 { 70 compatible = "marvell,mvebu-devbus"; 71 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 72 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 clocks = <&coreclk 0>; 76 status = "disabled"; 77 }; 78 79 devbus_cs2: devbus-cs2 { 80 compatible = "marvell,mvebu-devbus"; 81 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 82 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 clocks = <&coreclk 0>; 86 status = "disabled"; 87 }; 88 89 devbus_cs3: devbus-cs3 { 90 compatible = "marvell,mvebu-devbus"; 91 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 92 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 clocks = <&coreclk 0>; 96 status = "disabled"; 97 }; 98 99 internal-regs { 100 compatible = "simple-bus"; 101 u-boot,dm-pre-reloc; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 105 106 L2: cache-controller@8000 { 107 compatible = "arm,pl310-cache"; 108 reg = <0x8000 0x1000>; 109 cache-unified; 110 cache-level = <2>; 111 arm,double-linefill-incr = <0>; 112 arm,double-linefill-wrap = <0>; 113 arm,double-linefill = <0>; 114 prefetch-data = <1>; 115 }; 116 117 scu@c000 { 118 compatible = "arm,cortex-a9-scu"; 119 reg = <0xc000 0x58>; 120 }; 121 122 timer@c200 { 123 compatible = "arm,cortex-a9-global-timer"; 124 reg = <0xc200 0x20>; 125 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 126 clocks = <&coreclk 2>; 127 }; 128 129 timer@c600 { 130 compatible = "arm,cortex-a9-twd-timer"; 131 reg = <0xc600 0x20>; 132 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 133 clocks = <&coreclk 2>; 134 }; 135 136 gic: interrupt-controller@d000 { 137 compatible = "arm,cortex-a9-gic"; 138 #interrupt-cells = <3>; 139 #size-cells = <0>; 140 interrupt-controller; 141 reg = <0xd000 0x1000>, 142 <0xc100 0x100>; 143 }; 144 145 i2c0: i2c@11000 { 146 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 147 reg = <0x11000 0x20>; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 151 timeout-ms = <1000>; 152 clocks = <&coreclk 0>; 153 status = "disabled"; 154 }; 155 156 i2c1: i2c@11100 { 157 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 158 reg = <0x11100 0x20>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 162 timeout-ms = <1000>; 163 clocks = <&coreclk 0>; 164 status = "disabled"; 165 }; 166 167 uart0: serial@12000 { 168 compatible = "snps,dw-apb-uart"; 169 reg = <0x12000 0x100>; 170 reg-shift = <2>; 171 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 172 reg-io-width = <1>; 173 clocks = <&coreclk 0>; 174 status = "disabled"; 175 }; 176 177 uart1: serial@12100 { 178 compatible = "snps,dw-apb-uart"; 179 reg = <0x12100 0x100>; 180 reg-shift = <2>; 181 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 182 reg-io-width = <1>; 183 clocks = <&coreclk 0>; 184 status = "disabled"; 185 }; 186 187 pinctrl: pinctrl@18000 { 188 reg = <0x18000 0x20>; 189 190 ge0_rgmii_pins: ge-rgmii-pins-0 { 191 marvell,pins = "mpp6", "mpp7", "mpp8", 192 "mpp9", "mpp10", "mpp11", 193 "mpp12", "mpp13", "mpp14", 194 "mpp15", "mpp16", "mpp17"; 195 marvell,function = "ge0"; 196 }; 197 198 ge1_rgmii_pins: ge-rgmii-pins-1 { 199 marvell,pins = "mpp21", "mpp27", "mpp28", 200 "mpp29", "mpp30", "mpp31", 201 "mpp32", "mpp37", "mpp38", 202 "mpp39", "mpp40", "mpp41"; 203 marvell,function = "ge1"; 204 }; 205 206 i2c0_pins: i2c-pins-0 { 207 marvell,pins = "mpp2", "mpp3"; 208 marvell,function = "i2c0"; 209 }; 210 211 mdio_pins: mdio-pins { 212 marvell,pins = "mpp4", "mpp5"; 213 marvell,function = "ge"; 214 }; 215 216 ref_clk0_pins: ref-clk-pins-0 { 217 marvell,pins = "mpp45"; 218 marvell,function = "ref"; 219 }; 220 221 ref_clk1_pins: ref-clk-pins-1 { 222 marvell,pins = "mpp46"; 223 marvell,function = "ref"; 224 }; 225 226 spi0_pins: spi-pins-0 { 227 marvell,pins = "mpp22", "mpp23", "mpp24", 228 "mpp25"; 229 marvell,function = "spi0"; 230 }; 231 232 spi1_pins: spi-pins-1 { 233 marvell,pins = "mpp56", "mpp57", "mpp58", 234 "mpp59"; 235 marvell,function = "spi1"; 236 }; 237 238 nand_pins: nand-pins { 239 marvell,pins = "mpp22", "mpp34", "mpp23", 240 "mpp33", "mpp38", "mpp28", 241 "mpp40", "mpp42", "mpp35", 242 "mpp36", "mpp25", "mpp30", 243 "mpp32"; 244 marvell,function = "dev"; 245 }; 246 247 nand_rb: nand-rb { 248 marvell,pins = "mpp41"; 249 marvell,function = "nand"; 250 }; 251 252 uart0_pins: uart-pins-0 { 253 marvell,pins = "mpp0", "mpp1"; 254 marvell,function = "ua0"; 255 }; 256 257 uart1_pins: uart-pins-1 { 258 marvell,pins = "mpp19", "mpp20"; 259 marvell,function = "ua1"; 260 }; 261 262 sdhci_pins: sdhci-pins { 263 marvell,pins = "mpp48", "mpp49", "mpp50", 264 "mpp52", "mpp53", "mpp54", 265 "mpp55", "mpp57", "mpp58", 266 "mpp59"; 267 marvell,function = "sd0"; 268 }; 269 270 sata0_pins: sata-pins-0 { 271 marvell,pins = "mpp20"; 272 marvell,function = "sata0"; 273 }; 274 275 sata1_pins: sata-pins-1 { 276 marvell,pins = "mpp19"; 277 marvell,function = "sata1"; 278 }; 279 280 sata2_pins: sata-pins-2 { 281 marvell,pins = "mpp47"; 282 marvell,function = "sata2"; 283 }; 284 285 sata3_pins: sata-pins-3 { 286 marvell,pins = "mpp44"; 287 marvell,function = "sata3"; 288 }; 289 }; 290 291 gpio0: gpio@18100 { 292 compatible = "marvell,armada-370-gpio", 293 "marvell,orion-gpio"; 294 reg = <0x18100 0x40>, <0x181c0 0x08>; 295 reg-names = "gpio", "pwm"; 296 ngpios = <32>; 297 gpio-controller; 298 #gpio-cells = <2>; 299 #pwm-cells = <2>; 300 interrupt-controller; 301 #interrupt-cells = <2>; 302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&coreclk 0>; 307 }; 308 309 gpio1: gpio@18140 { 310 compatible = "marvell,armada-370-gpio", 311 "marvell,orion-gpio"; 312 reg = <0x18140 0x40>, <0x181c8 0x08>; 313 reg-names = "gpio", "pwm"; 314 ngpios = <28>; 315 gpio-controller; 316 #gpio-cells = <2>; 317 #pwm-cells = <2>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&coreclk 0>; 325 }; 326 327 systemc: system-controller@18200 { 328 compatible = "marvell,armada-380-system-controller", 329 "marvell,armada-370-xp-system-controller"; 330 reg = <0x18200 0x100>; 331 }; 332 333 gateclk: clock-gating-control@18220 { 334 compatible = "marvell,armada-380-gating-clock"; 335 reg = <0x18220 0x4>; 336 clocks = <&coreclk 0>; 337 #clock-cells = <1>; 338 }; 339 340 coreclk: mvebu-sar@18600 { 341 compatible = "marvell,armada-380-core-clock"; 342 reg = <0x18600 0x04>; 343 #clock-cells = <1>; 344 }; 345 346 mbusc: mbus-controller@20000 { 347 compatible = "marvell,mbus-controller"; 348 reg = <0x20000 0x100>, <0x20180 0x20>, 349 <0x20250 0x8>; 350 }; 351 352 mpic: interrupt-controller@20a00 { 353 compatible = "marvell,mpic"; 354 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 355 #interrupt-cells = <1>; 356 #size-cells = <1>; 357 interrupt-controller; 358 msi-controller; 359 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 360 }; 361 362 timer: timer@20300 { 363 compatible = "marvell,armada-380-timer", 364 "marvell,armada-xp-timer"; 365 reg = <0x20300 0x30>, <0x21040 0x30>; 366 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 367 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 368 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 369 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 370 <&mpic 5>, 371 <&mpic 6>; 372 clocks = <&coreclk 2>, <&refclk>; 373 clock-names = "nbclk", "fixed"; 374 }; 375 376 watchdog: watchdog@20300 { 377 compatible = "marvell,armada-380-wdt"; 378 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 379 clocks = <&coreclk 2>, <&refclk>; 380 clock-names = "nbclk", "fixed"; 381 }; 382 383 cpurst: cpurst@20800 { 384 compatible = "marvell,armada-370-cpu-reset"; 385 reg = <0x20800 0x10>; 386 }; 387 388 mpcore-soc-ctrl@20d20 { 389 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 390 reg = <0x20d20 0x6c>; 391 }; 392 393 coherencyfab: coherency-fabric@21010 { 394 compatible = "marvell,armada-380-coherency-fabric"; 395 reg = <0x21010 0x1c>; 396 }; 397 398 pmsu: pmsu@22000 { 399 compatible = "marvell,armada-380-pmsu"; 400 reg = <0x22000 0x1000>; 401 }; 402 403 /* 404 * As a special exception to the "order by 405 * register address" rule, the eth0 node is 406 * placed here to ensure that it gets 407 * registered as the first interface, since 408 * the network subsystem doesn't allow naming 409 * interfaces using DT aliases. Without this, 410 * the ordering of interfaces is different 411 * from the one used in U-Boot and the 412 * labeling of interfaces on the boards, which 413 * is very confusing for users. 414 */ 415 eth0: ethernet@70000 { 416 compatible = "marvell,armada-370-neta"; 417 reg = <0x70000 0x4000>; 418 interrupts-extended = <&mpic 8>; 419 clocks = <&gateclk 4>; 420 tx-csum-limit = <9800>; 421 status = "disabled"; 422 }; 423 424 eth1: ethernet@30000 { 425 compatible = "marvell,armada-370-neta"; 426 reg = <0x30000 0x4000>; 427 interrupts-extended = <&mpic 10>; 428 clocks = <&gateclk 3>; 429 status = "disabled"; 430 }; 431 432 eth2: ethernet@34000 { 433 compatible = "marvell,armada-370-neta"; 434 reg = <0x34000 0x4000>; 435 interrupts-extended = <&mpic 12>; 436 clocks = <&gateclk 2>; 437 status = "disabled"; 438 }; 439 440 usb0: usb@58000 { 441 compatible = "marvell,orion-ehci"; 442 reg = <0x58000 0x500>; 443 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&gateclk 18>; 445 status = "disabled"; 446 }; 447 448 xor0: xor@60800 { 449 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 450 reg = <0x60800 0x100 451 0x60a00 0x100>; 452 clocks = <&gateclk 22>; 453 status = "okay"; 454 455 xor00 { 456 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 457 dmacap,memcpy; 458 dmacap,xor; 459 }; 460 xor01 { 461 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 462 dmacap,memcpy; 463 dmacap,xor; 464 dmacap,memset; 465 }; 466 }; 467 468 xor1: xor@60900 { 469 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 470 reg = <0x60900 0x100 471 0x60b00 0x100>; 472 clocks = <&gateclk 28>; 473 status = "okay"; 474 475 xor10 { 476 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 477 dmacap,memcpy; 478 dmacap,xor; 479 }; 480 xor11 { 481 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 482 dmacap,memcpy; 483 dmacap,xor; 484 dmacap,memset; 485 }; 486 }; 487 488 mdio: mdio@72004 { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 compatible = "marvell,orion-mdio"; 492 reg = <0x72004 0x4>; 493 clocks = <&gateclk 4>; 494 }; 495 496 cesa: crypto@90000 { 497 compatible = "marvell,armada-38x-crypto"; 498 reg = <0x90000 0x10000>; 499 reg-names = "regs"; 500 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&gateclk 23>, <&gateclk 21>, 503 <&gateclk 14>, <&gateclk 16>; 504 clock-names = "cesa0", "cesa1", 505 "cesaz0", "cesaz1"; 506 marvell,crypto-srams = <&crypto_sram0>, 507 <&crypto_sram1>; 508 marvell,crypto-sram-size = <0x800>; 509 }; 510 511 rtc: rtc@a3800 { 512 compatible = "marvell,armada-380-rtc"; 513 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 514 reg-names = "rtc", "rtc-soc"; 515 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 516 }; 517 518 ahci0: sata@a8000 { 519 compatible = "marvell,armada-380-ahci"; 520 reg = <0xa8000 0x2000>; 521 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&gateclk 15>; 523 status = "disabled"; 524 }; 525 526 bm: bm@c8000 { 527 compatible = "marvell,armada-380-neta-bm"; 528 reg = <0xc8000 0xac>; 529 clocks = <&gateclk 13>; 530 internal-mem = <&bm_bppi>; 531 status = "disabled"; 532 }; 533 534 ahci1: sata@e0000 { 535 compatible = "marvell,armada-380-ahci"; 536 reg = <0xe0000 0x2000>; 537 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&gateclk 30>; 539 status = "disabled"; 540 }; 541 542 coredivclk: clock@e4250 { 543 compatible = "marvell,armada-380-corediv-clock"; 544 reg = <0xe4250 0xc>; 545 #clock-cells = <1>; 546 clocks = <&mainpll>; 547 clock-output-names = "nand"; 548 }; 549 550 thermal: thermal@e8078 { 551 compatible = "marvell,armada380-thermal"; 552 reg = <0xe4078 0x4>, <0xe4070 0x8>; 553 status = "okay"; 554 }; 555 556 nand_controller: nand-controller@d0000 { 557 compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand"; 558 reg = <0xd0000 0x54>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 562 clocks = <&coredivclk 0>; 563 status = "disabled"; 564 }; 565 566 sdhci: sdhci@d8000 { 567 compatible = "marvell,armada-380-sdhci"; 568 reg-names = "sdhci", "mbus", "conf-sdio3"; 569 reg = <0xd8000 0x1000>, 570 <0xdc000 0x100>, 571 <0x18454 0x4>; 572 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&gateclk 17>; 574 mrvl,clk-delay-cycles = <0x1F>; 575 status = "disabled"; 576 }; 577 578 usb3_0: usb3@f0000 { 579 compatible = "marvell,armada-380-xhci"; 580 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 581 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 582 clocks = <&gateclk 9>; 583 status = "disabled"; 584 }; 585 586 usb3_1: usb3@f8000 { 587 compatible = "marvell,armada-380-xhci"; 588 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 589 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&gateclk 10>; 591 status = "disabled"; 592 }; 593 }; 594 595 crypto_sram0: sa-sram0 { 596 compatible = "mmio-sram"; 597 reg = <MBUS_ID(0x09, 0x19) 0 0x800>; 598 clocks = <&gateclk 23>; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; 602 }; 603 604 crypto_sram1: sa-sram1 { 605 compatible = "mmio-sram"; 606 reg = <MBUS_ID(0x09, 0x15) 0 0x800>; 607 clocks = <&gateclk 21>; 608 #address-cells = <1>; 609 #size-cells = <1>; 610 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; 611 }; 612 613 bm_bppi: bm-bppi { 614 compatible = "mmio-sram"; 615 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 616 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 clocks = <&gateclk 13>; 620 no-memory-wc; 621 status = "disabled"; 622 }; 623 624 spi0: spi@10600 { 625 compatible = "marvell,armada-380-spi", 626 "marvell,orion-spi"; 627 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 628 #address-cells = <1>; 629 #size-cells = <0>; 630 cell-index = <0>; 631 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&coreclk 0>; 633 status = "disabled"; 634 }; 635 636 spi1: spi@10680 { 637 compatible = "marvell,armada-380-spi", 638 "marvell,orion-spi"; 639 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 cell-index = <1>; 643 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&coreclk 0>; 645 status = "disabled"; 646 }; 647 }; 648 649 clocks { 650 /* 1 GHz fixed main PLL */ 651 mainpll: mainpll { 652 compatible = "fixed-clock"; 653 #clock-cells = <0>; 654 clock-frequency = <1000000000>; 655 }; 656 657 /* 25 MHz reference crystal */ 658 refclk: oscillator { 659 compatible = "fixed-clock"; 660 #clock-cells = <0>; 661 clock-frequency = <25000000>; 662 }; 663 }; 664}; 665