1/*
2 * Device Tree file for the Guntermann & Drunck ControlCenter-Compact board
3 *
4 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
5 *
6 * based on the Device Tree file for Marvell Armada 388 evaluation board
7 * (DB-88F6820), which is
8 *
9 * Copyright (C) 2014 Marvell
10 *
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 *
13 * SPDX-License-Identifier:     GPL-2.0+
14 */
15
16/dts-v1/;
17
18#include "armada-388.dtsi"
19
20&gpio0 {
21	u-boot,dm-pre-reloc;
22};
23
24&gpio1 {
25	u-boot,dm-pre-reloc;
26};
27
28&uart0 {
29	u-boot,dm-pre-reloc;
30};
31
32&uart1 {
33	u-boot,dm-pre-reloc;
34};
35
36/ {
37	model = "Controlcenter Digital Compact";
38	compatible = "marvell,a385-db", "marvell,armada388",
39		"marvell,armada385", "marvell,armada380";
40
41	chosen {
42		bootargs = "console=ttyS1,115200 earlyprintk";
43		stdout-path = "/soc/internal-regs/serial@12100";
44	};
45
46	aliases {
47		ethernet0 = &eth0;
48		ethernet2 = &eth2;
49		mdio-gpio0 = &MDIO0;
50		mdio-gpio1 = &MDIO1;
51		mdio-gpio2 = &MDIO2;
52		spi0 = &spi0;
53		spi1 = &spi1;
54		i2c0 = &I2C0;
55		i2c1 = &I2C1;
56	};
57
58	memory {
59		device_type = "memory";
60		reg = <0x00000000 0x10000000>; /* 256 MB */
61	};
62
63	clocks {
64		sc16isclk: sc16isclk {
65			compatible = "fixed-clock";
66			#clock-cells = <0>;
67			clock-frequency = <11059200>;
68		};
69	};
70
71	soc {
72		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
73			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
74
75		internal-regs {
76			spi0: spi@10600 {
77				status = "okay";
78				sc16is741: sc16is741@0 {
79					compatible = "nxp,sc16is741";
80					reg = <0>;
81					clocks = <&sc16isclk>;
82					spi-max-frequency = <4000000>;
83					interrupt-parent = <&gpio0>;
84					interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
85					gpio-controller;
86					#gpio-cells = <2>;
87				};
88			};
89
90			spi1: spi@10680 {
91				status = "okay";
92				u-boot,dm-pre-reloc;
93				spi-flash@0 {
94					#address-cells = <1>;
95					#size-cells = <1>;
96					compatible = "n25q016a";
97					reg = <0>; /* Chip select 0 */
98					spi-max-frequency = <108000000>;
99				};
100				spi-flash@1 {
101					#address-cells = <1>;
102					#size-cells = <1>;
103					compatible = "n25q128a11";
104					reg = <1>; /* Chip select 1 */
105					spi-max-frequency = <108000000>;
106					u-boot,dm-pre-reloc;
107				};
108			};
109
110			I2C0: i2c@11000 {
111				status = "okay";
112				clock-frequency = <1000000>;
113				u-boot,dm-pre-reloc;
114				PCA21: pca9698@21 {
115					compatible = "nxp,pca9698";
116					reg = <0x21>;
117					#gpio-cells = <2>;
118					gpio-controller;
119				};
120				PCA22: pca9698@22 {
121					compatible = "nxp,pca9698";
122					u-boot,dm-pre-reloc;
123					reg = <0x22>;
124					#gpio-cells = <2>;
125					gpio-controller;
126				};
127				PCA23: pca9698@23 {
128					compatible = "nxp,pca9698";
129					reg = <0x23>;
130					#gpio-cells = <2>;
131					gpio-controller;
132				};
133				PCA24: pca9698@24 {
134					compatible = "nxp,pca9698";
135					reg = <0x24>;
136					#gpio-cells = <2>;
137					gpio-controller;
138				};
139				PCA25: pca9698@25 {
140					compatible = "nxp,pca9698";
141					reg = <0x25>;
142					#gpio-cells = <2>;
143					gpio-controller;
144				};
145				PCA26: pca9698@26 {
146					compatible = "nxp,pca9698";
147					reg = <0x26>;
148					#gpio-cells = <2>;
149					gpio-controller;
150				};
151			};
152
153			I2C1: i2c@11100 {
154				status = "okay";
155				clock-frequency = <400000>;
156				at97sc3205t@29 {
157					compatible = "atmel,at97sc3204t";
158					reg = <0x29>;
159					u-boot,i2c-offset-len = <0>;
160				};
161				emc2305@2d {
162					compatible = "smsc,emc2305";
163					#address-cells = <1>;
164					#size-cells = <0>;
165					reg = <0x2d>;
166					fan@0 {
167						reg = <0>;
168					};
169					fan@1 {
170						reg = <1>;
171					};
172					fan@2 {
173						reg = <2>;
174					};
175					fan@3 {
176						reg = <3>;
177					};
178					fan@4 {
179						reg = <4>;
180					};
181				};
182				lm77@48 {
183					compatible = "national,lm77";
184					reg = <0x48>;
185				};
186				ads1015@49 {
187					compatible = "ti,ads1015";
188					reg = <0x49>;
189				};
190				lm77@4a {
191					compatible = "national,lm77";
192					reg = <0x4a>;
193				};
194				ads1015@4b {
195					compatible = "ti,ads1015";
196					reg = <0x4b>;
197				};
198				emc2305@4c {
199					compatible = "smsc,emc2305";
200					#address-cells = <1>;
201					#size-cells = <0>;
202					reg = <0x4c>;
203					fan@0 {
204						reg = <0>;
205					};
206					fan@1 {
207						reg = <1>;
208					};
209					fan@2 {
210						reg = <2>;
211					};
212					fan@3 {
213						reg = <3>;
214					};
215					fan@4 {
216						reg = <4>;
217					};
218				};
219				at24c512@54 {
220					compatible = "atmel,24c512";
221					reg = <0x54>;
222					u-boot,i2c-offset-len = <2>;
223				};
224				ds1339@68 {
225					compatible = "dallas,ds1339";
226					reg = <0x68>;
227				};
228			};
229
230			serial@12000 {
231				status = "okay";
232			};
233
234			serial@12100 {
235				status = "okay";
236			};
237
238			ethernet@34000 {
239				status = "okay";
240				phy = <&phy1>;
241				phy-mode = "sgmii";
242			};
243
244			usb@58000 {
245				status = "ok";
246			};
247
248			ethernet@70000 {
249				status = "okay";
250				phy = <&phy0>;
251				phy-mode = "sgmii";
252			};
253
254			mdio@72004 {
255				phy0: ethernet-phy@0 {
256					reg = <1>;
257				};
258
259				phy1: ethernet-phy@1 {
260					reg = <0>;
261				};
262			};
263
264			sata@a8000 {
265				status = "okay";
266			};
267
268			sdhci@d8000 {
269				broken-cd;
270				wp-inverted;
271				bus-width = <4>;
272				status = "okay";
273				no-1-8-v;
274			};
275
276			usb3@f0000 {
277				status = "okay";
278			};
279		};
280
281		pcie-controller {
282			status = "okay";
283			/*
284			 * The two PCIe units are accessible through
285			 * standard PCIe slots on the board.
286			 */
287			pcie@3,0 {
288				/* Port 0, Lane 0 */
289				status = "okay";
290			};
291		};
292
293		MDIO0: mdio0 {
294			compatible = "virtual,mdio-gpio";
295			#address-cells = <1>;
296			#size-cells = <0>;
297			gpios = < /*MDC*/ &gpio0 13 0
298				  /*MDIO*/ &gpio0 14 0>;
299			mv88e1240@0 {
300				reg = <0x0>;
301			};
302			mv88e1240@1 {
303				reg = <0x1>;
304			};
305			mv88e1240@2 {
306				reg = <0x2>;
307			};
308			mv88e1240@3 {
309				reg = <0x3>;
310			};
311			mv88e1240@4 {
312				reg = <0x4>;
313			};
314			mv88e1240@5 {
315				reg = <0x5>;
316			};
317			mv88e1240@6 {
318				reg = <0x6>;
319			};
320			mv88e1240@7 {
321				reg = <0x7>;
322			};
323			mv88e1240@8 {
324				reg = <0x8>;
325			};
326			mv88e1240@9 {
327				reg = <0x9>;
328			};
329			mv88e1240@a {
330				reg = <0xa>;
331			};
332			mv88e1240@b {
333				reg = <0xb>;
334			};
335			mv88e1240@c {
336				reg = <0xc>;
337			};
338			mv88e1240@d {
339				reg = <0xd>;
340			};
341			mv88e1240@e {
342				reg = <0xe>;
343			};
344			mv88e1240@f {
345				reg = <0xf>;
346			};
347			mv88e1240@10 {
348				reg = <0x10>;
349			};
350			mv88e1240@11 {
351				reg = <0x11>;
352			};
353			mv88e1240@12 {
354				reg = <0x12>;
355			};
356			mv88e1240@13 {
357				reg = <0x13>;
358			};
359			mv88e1240@14 {
360				reg = <0x14>;
361			};
362			mv88e1240@15 {
363				reg = <0x15>;
364			};
365			mv88e1240@16 {
366				reg = <0x16>;
367			};
368			mv88e1240@17 {
369				reg = <0x17>;
370			};
371			mv88e1240@18 {
372				reg = <0x18>;
373			};
374			mv88e1240@19 {
375				reg = <0x19>;
376			};
377			mv88e1240@1a {
378				reg = <0x1a>;
379			};
380			mv88e1240@1b {
381				reg = <0x1b>;
382			};
383			mv88e1240@1c {
384				reg = <0x1c>;
385			};
386			mv88e1240@1d {
387				reg = <0x1d>;
388			};
389			mv88e1240@1e {
390				reg = <0x1e>;
391			};
392			mv88e1240@1f {
393				reg = <0x1f>;
394			};
395		};
396
397		MDIO1: mdio1 {
398			compatible = "virtual,mdio-gpio";
399			#address-cells = <1>;
400			#size-cells = <0>;
401			gpios = < /*MDC*/ &gpio0 25 0
402				  /*MDIO*/ &gpio1 13 0>;
403			mv88e1240@0 {
404				reg = <0x0>;
405			};
406			mv88e1240@1 {
407				reg = <0x1>;
408			};
409			mv88e1240@2 {
410				reg = <0x2>;
411			};
412			mv88e1240@3 {
413				reg = <0x3>;
414			};
415			mv88e1240@4 {
416				reg = <0x4>;
417			};
418			mv88e1240@5 {
419				reg = <0x5>;
420			};
421			mv88e1240@6 {
422				reg = <0x6>;
423			};
424			mv88e1240@7 {
425				reg = <0x7>;
426			};
427			mv88e1240@8 {
428				reg = <0x8>;
429			};
430			mv88e1240@9 {
431				reg = <0x9>;
432			};
433			mv88e1240@a {
434				reg = <0xa>;
435			};
436			mv88e1240@b {
437				reg = <0xb>;
438			};
439			mv88e1240@c {
440				reg = <0xc>;
441			};
442			mv88e1240@d {
443				reg = <0xd>;
444			};
445			mv88e1240@e {
446				reg = <0xe>;
447			};
448			mv88e1240@f {
449				reg = <0xf>;
450			};
451			mv88e1240@10 {
452				reg = <0x10>;
453			};
454			mv88e1240@11 {
455				reg = <0x11>;
456			};
457			mv88e1240@12 {
458				reg = <0x12>;
459			};
460			mv88e1240@13 {
461				reg = <0x13>;
462			};
463			mv88e1240@14 {
464				reg = <0x14>;
465			};
466			mv88e1240@15 {
467				reg = <0x15>;
468			};
469			mv88e1240@16 {
470				reg = <0x16>;
471			};
472			mv88e1240@17 {
473				reg = <0x17>;
474			};
475			mv88e1240@18 {
476				reg = <0x18>;
477			};
478			mv88e1240@19 {
479				reg = <0x19>;
480			};
481			mv88e1240@1a {
482				reg = <0x1a>;
483			};
484			mv88e1240@1b {
485				reg = <0x1b>;
486			};
487			mv88e1240@1c {
488				reg = <0x1c>;
489			};
490			mv88e1240@1d {
491				reg = <0x1d>;
492			};
493			mv88e1240@1e {
494				reg = <0x1e>;
495			};
496			mv88e1240@1f {
497				reg = <0x1f>;
498			};
499		};
500
501		MDIO2: mdio2 {
502			compatible = "virtual,mdio-gpio";
503			#address-cells = <1>;
504			#size-cells = <0>;
505			gpios = < /*MDC*/ &gpio1 14 0
506				  /*MDIO*/ &gpio0 24 0>;
507			mv88e1240@0 {
508				reg = <0x0>;
509			};
510			mv88e1240@1 {
511				reg = <0x1>;
512			};
513			mv88e1240@2 {
514				reg = <0x2>;
515			};
516			mv88e1240@3 {
517				reg = <0x3>;
518			};
519			mv88e1240@4 {
520				reg = <0x4>;
521			};
522			mv88e1240@5 {
523				reg = <0x5>;
524			};
525			mv88e1240@6 {
526				reg = <0x6>;
527			};
528			mv88e1240@7 {
529				reg = <0x7>;
530			};
531			mv88e1240@8 {
532				reg = <0x8>;
533			};
534			mv88e1240@9 {
535				reg = <0x9>;
536			};
537			mv88e1240@a {
538				reg = <0xa>;
539			};
540			mv88e1240@b {
541				reg = <0xb>;
542			};
543			mv88e1240@c {
544				reg = <0xc>;
545			};
546			mv88e1240@d {
547				reg = <0xd>;
548			};
549			mv88e1240@e {
550				reg = <0xe>;
551			};
552			mv88e1240@f {
553				reg = <0xf>;
554			};
555			mv88e1240@10 {
556				reg = <0x10>;
557			};
558			mv88e1240@11 {
559				reg = <0x11>;
560			};
561			mv88e1240@12 {
562				reg = <0x12>;
563			};
564			mv88e1240@13 {
565				reg = <0x13>;
566			};
567			mv88e1240@14 {
568				reg = <0x14>;
569			};
570			mv88e1240@15 {
571				reg = <0x15>;
572			};
573		};
574	};
575
576	leds {
577		compatible = "gpio-leds";
578
579		finder_led {
580			label = "finder-led";
581			gpios = <&PCA22 25 0>;
582		};
583
584		status_led {
585			label = "status-led";
586			gpios = <&gpio0 29 0>;
587		};
588	};
589};
590