1/* 2 * Device Tree file for Marvell Armada 385 development board 3 * (RD-88F6820-GP) 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPL or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This file is licensed under the terms of the GNU General Public 15 * License version 2. This program is licensed "as is" without 16 * any warranty of any kind, whether express or implied. 17 * 18 * Or, alternatively, 19 * 20 * b) Permission is hereby granted, free of charge, to any person 21 * obtaining a copy of this software and associated documentation 22 * files (the "Software"), to deal in the Software without 23 * restriction, including without limitation the rights to use, 24 * copy, modify, merge, publish, distribute, sublicense, and/or 25 * sell copies of the Software, and to permit persons to whom the 26 * Software is furnished to do so, subject to the following 27 * conditions: 28 * 29 * The above copyright notice and this permission notice shall be 30 * included in all copies or substantial portions of the Software. 31 * 32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39 * OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42/dts-v1/; 43#include "armada-388.dtsi" 44#include <dt-bindings/gpio/gpio.h> 45 46/ { 47 model = "Marvell Armada 385 GP"; 48 compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; 49 50 chosen { 51 stdout-path = "serial0:115200n8"; 52 }; 53 54 aliases { 55 ethernet0 = ð0; 56 ethernet1 = ð1; 57 spi0 = &spi0; 58 }; 59 60 memory { 61 device_type = "memory"; 62 reg = <0x00000000 0x80000000>; /* 2 GB */ 63 }; 64 65 soc { 66 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 67 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 68 69 internal-regs { 70 spi@10600 { 71 pinctrl-names = "default"; 72 pinctrl-0 = <&spi0_pins>; 73 status = "okay"; 74 u-boot,dm-pre-reloc; 75 76 spi-flash@0 { 77 u-boot,dm-pre-reloc; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 compatible = "st,m25p128", "jedec,spi-nor"; 81 reg = <0>; /* Chip select 0 */ 82 spi-max-frequency = <50000000>; 83 m25p,fast-read; 84 }; 85 }; 86 87 i2c@11000 { 88 pinctrl-names = "default"; 89 pinctrl-0 = <&i2c0_pins>; 90 status = "okay"; 91 clock-frequency = <100000>; 92 /* 93 * The EEPROM located at adresse 54 is needed 94 * for the boot - DO NOT ERASE IT - 95 */ 96 97 expander0: pca9555@20 { 98 compatible = "nxp,pca9555"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pca0_pins>; 101 interrupt-parent = <&gpio0>; 102 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 103 gpio-controller; 104 #gpio-cells = <2>; 105 interrupt-controller; 106 #interrupt-cells = <2>; 107 reg = <0x20>; 108 }; 109 110 expander1: pca9555@21 { 111 compatible = "nxp,pca9555"; 112 pinctrl-names = "default"; 113 interrupt-parent = <&gpio0>; 114 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 115 gpio-controller; 116 #gpio-cells = <2>; 117 interrupt-controller; 118 #interrupt-cells = <2>; 119 reg = <0x21>; 120 }; 121 122 }; 123 124 serial@12000 { 125 /* 126 * Exported on the micro USB connector CON16 127 * through an FTDI 128 */ 129 130 pinctrl-names = "default"; 131 pinctrl-0 = <&uart0_pins>; 132 status = "okay"; 133 u-boot,dm-pre-reloc; 134 }; 135 136 /* GE1 CON15 */ 137 ethernet@30000 { 138 pinctrl-names = "default"; 139 pinctrl-0 = <&ge1_rgmii_pins>; 140 status = "okay"; 141 phy = <&phy1>; 142 phy-mode = "rgmii-id"; 143 }; 144 145 /* CON4 */ 146 usb@58000 { 147 vcc-supply = <®_usb2_0_vbus>; 148 status = "okay"; 149 }; 150 151 /* GE0 CON1 */ 152 ethernet@70000 { 153 pinctrl-names = "default"; 154 /* 155 * The Reference Clock 0 is used to provide a 156 * clock to the PHY 157 */ 158 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; 159 status = "okay"; 160 phy = <&phy0>; 161 phy-mode = "rgmii-id"; 162 }; 163 164 165 mdio@72004 { 166 pinctrl-names = "default"; 167 pinctrl-0 = <&mdio_pins>; 168 169 phy0: ethernet-phy@1 { 170 reg = <1>; 171 }; 172 173 phy1: ethernet-phy@0 { 174 reg = <0>; 175 }; 176 }; 177 178 sata@a8000 { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&sata0_pins>, <&sata1_pins>; 181 status = "okay"; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 185 sata0: sata-port@0 { 186 reg = <0>; 187 target-supply = <®_5v_sata0>; 188 }; 189 190 sata1: sata-port@1 { 191 reg = <1>; 192 target-supply = <®_5v_sata1>; 193 }; 194 }; 195 196 sata@e0000 { 197 pinctrl-names = "default"; 198 pinctrl-0 = <&sata2_pins>, <&sata3_pins>; 199 status = "okay"; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 203 sata2: sata-port@0 { 204 reg = <0>; 205 target-supply = <®_5v_sata2>; 206 }; 207 208 sata3: sata-port@1 { 209 reg = <1>; 210 target-supply = <®_5v_sata3>; 211 }; 212 }; 213 214 sdhci@d8000 { 215 pinctrl-names = "default"; 216 pinctrl-0 = <&sdhci_pins>; 217 cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; 218 no-1-8-v; 219 wp-inverted; 220 bus-width = <8>; 221 status = "okay"; 222 }; 223 224 /* CON5 */ 225 usb3@f0000 { 226 vcc-supply = <®_usb2_1_vbus>; 227 status = "okay"; 228 }; 229 230 /* CON7 */ 231 usb3@f8000 { 232 vcc-supply = <®_usb3_vbus>; 233 status = "okay"; 234 }; 235 }; 236 237 pcie { 238 status = "okay"; 239 /* 240 * One PCIe units is accessible through 241 * standard PCIe slot on the board. 242 */ 243 pcie@1,0 { 244 /* Port 0, Lane 0 */ 245 status = "okay"; 246 }; 247 248 /* 249 * The two other PCIe units are accessible 250 * through mini PCIe slot on the board. 251 */ 252 pcie@2,0 { 253 /* Port 1, Lane 0 */ 254 status = "okay"; 255 }; 256 pcie@3,0 { 257 /* Port 2, Lane 0 */ 258 status = "okay"; 259 }; 260 }; 261 262 gpio-fan { 263 compatible = "gpio-fan"; 264 gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; 265 gpio-fan,speed-map = < 0 0 266 3000 1>; 267 }; 268 }; 269 270 reg_usb3_vbus: usb3-vbus { 271 compatible = "regulator-fixed"; 272 regulator-name = "usb3-vbus"; 273 regulator-min-microvolt = <5000000>; 274 regulator-max-microvolt = <5000000>; 275 enable-active-high; 276 regulator-always-on; 277 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; 278 }; 279 280 reg_usb2_0_vbus: v5-vbus0 { 281 compatible = "regulator-fixed"; 282 regulator-name = "v5.0-vbus0"; 283 regulator-min-microvolt = <5000000>; 284 regulator-max-microvolt = <5000000>; 285 enable-active-high; 286 regulator-always-on; 287 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; 288 }; 289 290 reg_usb2_1_vbus: v5-vbus1 { 291 compatible = "regulator-fixed"; 292 regulator-name = "v5.0-vbus1"; 293 regulator-min-microvolt = <5000000>; 294 regulator-max-microvolt = <5000000>; 295 enable-active-high; 296 regulator-always-on; 297 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; 298 }; 299 300 reg_usb2_1_vbus: v5-vbus1 { 301 compatible = "regulator-fixed"; 302 regulator-name = "v5.0-vbus1"; 303 regulator-min-microvolt = <5000000>; 304 regulator-max-microvolt = <5000000>; 305 enable-active-high; 306 regulator-always-on; 307 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; 308 }; 309 310 reg_sata0: pwr-sata0 { 311 compatible = "regulator-fixed"; 312 regulator-name = "pwr_en_sata0"; 313 enable-active-high; 314 regulator-always-on; 315 316 }; 317 318 reg_5v_sata0: v5-sata0 { 319 compatible = "regulator-fixed"; 320 regulator-name = "v5.0-sata0"; 321 regulator-min-microvolt = <5000000>; 322 regulator-max-microvolt = <5000000>; 323 regulator-always-on; 324 vin-supply = <®_sata0>; 325 }; 326 327 reg_12v_sata0: v12-sata0 { 328 compatible = "regulator-fixed"; 329 regulator-name = "v12.0-sata0"; 330 regulator-min-microvolt = <12000000>; 331 regulator-max-microvolt = <12000000>; 332 regulator-always-on; 333 vin-supply = <®_sata0>; 334 }; 335 336 reg_sata1: pwr-sata1 { 337 regulator-name = "pwr_en_sata1"; 338 compatible = "regulator-fixed"; 339 regulator-min-microvolt = <12000000>; 340 regulator-max-microvolt = <12000000>; 341 enable-active-high; 342 regulator-always-on; 343 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 344 }; 345 346 reg_5v_sata1: v5-sata1 { 347 compatible = "regulator-fixed"; 348 regulator-name = "v5.0-sata1"; 349 regulator-min-microvolt = <5000000>; 350 regulator-max-microvolt = <5000000>; 351 regulator-always-on; 352 vin-supply = <®_sata1>; 353 }; 354 355 reg_12v_sata1: v12-sata1 { 356 compatible = "regulator-fixed"; 357 regulator-name = "v12.0-sata1"; 358 regulator-min-microvolt = <12000000>; 359 regulator-max-microvolt = <12000000>; 360 regulator-always-on; 361 vin-supply = <®_sata1>; 362 }; 363 364 reg_sata2: pwr-sata2 { 365 compatible = "regulator-fixed"; 366 regulator-name = "pwr_en_sata2"; 367 enable-active-high; 368 regulator-always-on; 369 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; 370 }; 371 372 reg_5v_sata2: v5-sata2 { 373 compatible = "regulator-fixed"; 374 regulator-name = "v5.0-sata2"; 375 regulator-min-microvolt = <5000000>; 376 regulator-max-microvolt = <5000000>; 377 regulator-always-on; 378 vin-supply = <®_sata2>; 379 }; 380 381 reg_12v_sata2: v12-sata2 { 382 compatible = "regulator-fixed"; 383 regulator-name = "v12.0-sata2"; 384 regulator-min-microvolt = <12000000>; 385 regulator-max-microvolt = <12000000>; 386 regulator-always-on; 387 vin-supply = <®_sata2>; 388 }; 389 390 reg_sata3: pwr-sata3 { 391 compatible = "regulator-fixed"; 392 regulator-name = "pwr_en_sata3"; 393 enable-active-high; 394 regulator-always-on; 395 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 396 }; 397 398 reg_5v_sata3: v5-sata3 { 399 compatible = "regulator-fixed"; 400 regulator-name = "v5.0-sata3"; 401 regulator-min-microvolt = <5000000>; 402 regulator-max-microvolt = <5000000>; 403 regulator-always-on; 404 vin-supply = <®_sata3>; 405 }; 406 407 reg_12v_sata3: v12-sata3 { 408 compatible = "regulator-fixed"; 409 regulator-name = "v12.0-sata3"; 410 regulator-min-microvolt = <12000000>; 411 regulator-max-microvolt = <12000000>; 412 regulator-always-on; 413 vin-supply = <®_sata3>; 414 }; 415}; 416 417&pinctrl { 418 pca0_pins: pca0_pins { 419 marvell,pins = "mpp18"; 420 marvell,function = "gpio"; 421 }; 422}; 423