1/* 2 * Device Tree file for Marvell Armada 385 development board 3 * (RD-88F6820-GP) 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPL or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This file is licensed under the terms of the GNU General Public 15 * License version 2. This program is licensed "as is" without 16 * any warranty of any kind, whether express or implied. 17 * 18 * Or, alternatively, 19 * 20 * b) Permission is hereby granted, free of charge, to any person 21 * obtaining a copy of this software and associated documentation 22 * files (the "Software"), to deal in the Software without 23 * restriction, including without limitation the rights to use, 24 * copy, modify, merge, publish, distribute, sublicense, and/or 25 * sell copies of the Software, and to permit persons to whom the 26 * Software is furnished to do so, subject to the following 27 * conditions: 28 * 29 * The above copyright notice and this permission notice shall be 30 * included in all copies or substantial portions of the Software. 31 * 32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39 * OTHER DEALINGS IN THE SOFTWARE. 40 */ 41 42/dts-v1/; 43#include "armada-388.dtsi" 44#include <dt-bindings/gpio/gpio.h> 45 46/ { 47 model = "Marvell Armada 385 GP"; 48 compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; 49 50 chosen { 51 stdout-path = "serial0:115200n8"; 52 }; 53 54 memory { 55 device_type = "memory"; 56 reg = <0x00000000 0x80000000>; /* 2 GB */ 57 }; 58 59 soc { 60 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 61 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 62 63 internal-regs { 64 spi@10600 { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&spi0_pins>; 67 status = "okay"; 68 69 spi-flash@0 { 70 #address-cells = <1>; 71 #size-cells = <1>; 72 compatible = "st,m25p128", "jedec,spi-nor"; 73 reg = <0>; /* Chip select 0 */ 74 spi-max-frequency = <50000000>; 75 m25p,fast-read; 76 }; 77 }; 78 79 i2c@11000 { 80 pinctrl-names = "default"; 81 pinctrl-0 = <&i2c0_pins>; 82 status = "okay"; 83 clock-frequency = <100000>; 84 /* 85 * The EEPROM located at adresse 54 is needed 86 * for the boot - DO NOT ERASE IT - 87 */ 88 89 expander0: pca9555@20 { 90 compatible = "nxp,pca9555"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pca0_pins>; 93 interrupt-parent = <&gpio0>; 94 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 95 gpio-controller; 96 #gpio-cells = <2>; 97 interrupt-controller; 98 #interrupt-cells = <2>; 99 reg = <0x20>; 100 }; 101 102 expander1: pca9555@21 { 103 compatible = "nxp,pca9555"; 104 pinctrl-names = "default"; 105 interrupt-parent = <&gpio0>; 106 interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 107 gpio-controller; 108 #gpio-cells = <2>; 109 interrupt-controller; 110 #interrupt-cells = <2>; 111 reg = <0x21>; 112 }; 113 114 }; 115 116 serial@12000 { 117 /* 118 * Exported on the micro USB connector CON16 119 * through an FTDI 120 */ 121 122 pinctrl-names = "default"; 123 pinctrl-0 = <&uart0_pins>; 124 status = "okay"; 125 }; 126 127 /* GE1 CON15 */ 128 ethernet@30000 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&ge1_rgmii_pins>; 131 status = "okay"; 132 phy = <&phy1>; 133 phy-mode = "rgmii-id"; 134 }; 135 136 /* CON4 */ 137 usb@58000 { 138 vcc-supply = <®_usb2_0_vbus>; 139 status = "okay"; 140 }; 141 142 /* GE0 CON1 */ 143 ethernet@70000 { 144 pinctrl-names = "default"; 145 /* 146 * The Reference Clock 0 is used to provide a 147 * clock to the PHY 148 */ 149 pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; 150 status = "okay"; 151 phy = <&phy0>; 152 phy-mode = "rgmii-id"; 153 }; 154 155 156 mdio@72004 { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&mdio_pins>; 159 160 phy0: ethernet-phy@1 { 161 reg = <1>; 162 }; 163 164 phy1: ethernet-phy@0 { 165 reg = <0>; 166 }; 167 }; 168 169 sata@a8000 { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&sata0_pins>, <&sata1_pins>; 172 status = "okay"; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 sata0: sata-port@0 { 177 reg = <0>; 178 target-supply = <®_5v_sata0>; 179 }; 180 181 sata1: sata-port@1 { 182 reg = <1>; 183 target-supply = <®_5v_sata1>; 184 }; 185 }; 186 187 sata@e0000 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&sata2_pins>, <&sata3_pins>; 190 status = "okay"; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 194 sata2: sata-port@0 { 195 reg = <0>; 196 target-supply = <®_5v_sata2>; 197 }; 198 199 sata3: sata-port@1 { 200 reg = <1>; 201 target-supply = <®_5v_sata3>; 202 }; 203 }; 204 205 sdhci@d8000 { 206 pinctrl-names = "default"; 207 pinctrl-0 = <&sdhci_pins>; 208 cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; 209 no-1-8-v; 210 wp-inverted; 211 bus-width = <8>; 212 status = "okay"; 213 }; 214 215 /* CON5 */ 216 usb3@f0000 { 217 vcc-supply = <®_usb2_1_vbus>; 218 status = "okay"; 219 }; 220 221 /* CON7 */ 222 usb3@f8000 { 223 vcc-supply = <®_usb3_vbus>; 224 status = "okay"; 225 }; 226 }; 227 228 pcie-controller { 229 status = "okay"; 230 /* 231 * One PCIe units is accessible through 232 * standard PCIe slot on the board. 233 */ 234 pcie@1,0 { 235 /* Port 0, Lane 0 */ 236 status = "okay"; 237 }; 238 239 /* 240 * The two other PCIe units are accessible 241 * through mini PCIe slot on the board. 242 */ 243 pcie@2,0 { 244 /* Port 1, Lane 0 */ 245 status = "okay"; 246 }; 247 pcie@3,0 { 248 /* Port 2, Lane 0 */ 249 status = "okay"; 250 }; 251 }; 252 253 gpio-fan { 254 compatible = "gpio-fan"; 255 gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; 256 gpio-fan,speed-map = < 0 0 257 3000 1>; 258 }; 259 }; 260 261 reg_usb3_vbus: usb3-vbus { 262 compatible = "regulator-fixed"; 263 regulator-name = "usb3-vbus"; 264 regulator-min-microvolt = <5000000>; 265 regulator-max-microvolt = <5000000>; 266 enable-active-high; 267 regulator-always-on; 268 gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; 269 }; 270 271 reg_usb2_0_vbus: v5-vbus0 { 272 compatible = "regulator-fixed"; 273 regulator-name = "v5.0-vbus0"; 274 regulator-min-microvolt = <5000000>; 275 regulator-max-microvolt = <5000000>; 276 enable-active-high; 277 regulator-always-on; 278 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; 279 }; 280 281 reg_usb2_1_vbus: v5-vbus1 { 282 compatible = "regulator-fixed"; 283 regulator-name = "v5.0-vbus1"; 284 regulator-min-microvolt = <5000000>; 285 regulator-max-microvolt = <5000000>; 286 enable-active-high; 287 regulator-always-on; 288 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; 289 }; 290 291 reg_usb2_1_vbus: v5-vbus1 { 292 compatible = "regulator-fixed"; 293 regulator-name = "v5.0-vbus1"; 294 regulator-min-microvolt = <5000000>; 295 regulator-max-microvolt = <5000000>; 296 enable-active-high; 297 regulator-always-on; 298 gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; 299 }; 300 301 reg_sata0: pwr-sata0 { 302 compatible = "regulator-fixed"; 303 regulator-name = "pwr_en_sata0"; 304 enable-active-high; 305 regulator-always-on; 306 307 }; 308 309 reg_5v_sata0: v5-sata0 { 310 compatible = "regulator-fixed"; 311 regulator-name = "v5.0-sata0"; 312 regulator-min-microvolt = <5000000>; 313 regulator-max-microvolt = <5000000>; 314 regulator-always-on; 315 vin-supply = <®_sata0>; 316 }; 317 318 reg_12v_sata0: v12-sata0 { 319 compatible = "regulator-fixed"; 320 regulator-name = "v12.0-sata0"; 321 regulator-min-microvolt = <12000000>; 322 regulator-max-microvolt = <12000000>; 323 regulator-always-on; 324 vin-supply = <®_sata0>; 325 }; 326 327 reg_sata1: pwr-sata1 { 328 regulator-name = "pwr_en_sata1"; 329 compatible = "regulator-fixed"; 330 regulator-min-microvolt = <12000000>; 331 regulator-max-microvolt = <12000000>; 332 enable-active-high; 333 regulator-always-on; 334 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 335 }; 336 337 reg_5v_sata1: v5-sata1 { 338 compatible = "regulator-fixed"; 339 regulator-name = "v5.0-sata1"; 340 regulator-min-microvolt = <5000000>; 341 regulator-max-microvolt = <5000000>; 342 regulator-always-on; 343 vin-supply = <®_sata1>; 344 }; 345 346 reg_12v_sata1: v12-sata1 { 347 compatible = "regulator-fixed"; 348 regulator-name = "v12.0-sata1"; 349 regulator-min-microvolt = <12000000>; 350 regulator-max-microvolt = <12000000>; 351 regulator-always-on; 352 vin-supply = <®_sata1>; 353 }; 354 355 reg_sata2: pwr-sata2 { 356 compatible = "regulator-fixed"; 357 regulator-name = "pwr_en_sata2"; 358 enable-active-high; 359 regulator-always-on; 360 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; 361 }; 362 363 reg_5v_sata2: v5-sata2 { 364 compatible = "regulator-fixed"; 365 regulator-name = "v5.0-sata2"; 366 regulator-min-microvolt = <5000000>; 367 regulator-max-microvolt = <5000000>; 368 regulator-always-on; 369 vin-supply = <®_sata2>; 370 }; 371 372 reg_12v_sata2: v12-sata2 { 373 compatible = "regulator-fixed"; 374 regulator-name = "v12.0-sata2"; 375 regulator-min-microvolt = <12000000>; 376 regulator-max-microvolt = <12000000>; 377 regulator-always-on; 378 vin-supply = <®_sata2>; 379 }; 380 381 reg_sata3: pwr-sata3 { 382 compatible = "regulator-fixed"; 383 regulator-name = "pwr_en_sata3"; 384 enable-active-high; 385 regulator-always-on; 386 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 387 }; 388 389 reg_5v_sata3: v5-sata3 { 390 compatible = "regulator-fixed"; 391 regulator-name = "v5.0-sata3"; 392 regulator-min-microvolt = <5000000>; 393 regulator-max-microvolt = <5000000>; 394 regulator-always-on; 395 vin-supply = <®_sata3>; 396 }; 397 398 reg_12v_sata3: v12-sata3 { 399 compatible = "regulator-fixed"; 400 regulator-name = "v12.0-sata3"; 401 regulator-min-microvolt = <12000000>; 402 regulator-max-microvolt = <12000000>; 403 regulator-always-on; 404 vin-supply = <®_sata3>; 405 }; 406}; 407 408&pinctrl { 409 pca0_pins: pca0_pins { 410 marvell,pins = "mpp18"; 411 marvell,function = "gpio"; 412 }; 413}; 414