1*39a230aaSStefan Roese/* 2*39a230aaSStefan Roese * Device Tree file for Marvell Armada 385 development board 3*39a230aaSStefan Roese * (RD-88F6820-GP) 4*39a230aaSStefan Roese * 5*39a230aaSStefan Roese * Copyright (C) 2014 Marvell 6*39a230aaSStefan Roese * 7*39a230aaSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 8*39a230aaSStefan Roese * 9*39a230aaSStefan Roese * This file is dual-licensed: you can use it either under the terms 10*39a230aaSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 11*39a230aaSStefan Roese * licensing only applies to this file, and not this project as a 12*39a230aaSStefan Roese * whole. 13*39a230aaSStefan Roese * 14*39a230aaSStefan Roese * a) This file is licensed under the terms of the GNU General Public 15*39a230aaSStefan Roese * License version 2. This program is licensed "as is" without 16*39a230aaSStefan Roese * any warranty of any kind, whether express or implied. 17*39a230aaSStefan Roese * 18*39a230aaSStefan Roese * Or, alternatively, 19*39a230aaSStefan Roese * 20*39a230aaSStefan Roese * b) Permission is hereby granted, free of charge, to any person 21*39a230aaSStefan Roese * obtaining a copy of this software and associated documentation 22*39a230aaSStefan Roese * files (the "Software"), to deal in the Software without 23*39a230aaSStefan Roese * restriction, including without limitation the rights to use, 24*39a230aaSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 25*39a230aaSStefan Roese * sell copies of the Software, and to permit persons to whom the 26*39a230aaSStefan Roese * Software is furnished to do so, subject to the following 27*39a230aaSStefan Roese * conditions: 28*39a230aaSStefan Roese * 29*39a230aaSStefan Roese * The above copyright notice and this permission notice shall be 30*39a230aaSStefan Roese * included in all copies or substantial portions of the Software. 31*39a230aaSStefan Roese * 32*39a230aaSStefan Roese * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 33*39a230aaSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 34*39a230aaSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 35*39a230aaSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 36*39a230aaSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 37*39a230aaSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 38*39a230aaSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 39*39a230aaSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 40*39a230aaSStefan Roese */ 41*39a230aaSStefan Roese 42*39a230aaSStefan Roese/dts-v1/; 43*39a230aaSStefan Roese#include "armada-388.dtsi" 44*39a230aaSStefan Roese#include <dt-bindings/gpio/gpio.h> 45*39a230aaSStefan Roese 46*39a230aaSStefan Roese/ { 47*39a230aaSStefan Roese model = "Marvell Armada 385 GP"; 48*39a230aaSStefan Roese compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380"; 49*39a230aaSStefan Roese 50*39a230aaSStefan Roese chosen { 51*39a230aaSStefan Roese stdout-path = "serial0:115200n8"; 52*39a230aaSStefan Roese }; 53*39a230aaSStefan Roese 54*39a230aaSStefan Roese memory { 55*39a230aaSStefan Roese device_type = "memory"; 56*39a230aaSStefan Roese reg = <0x00000000 0x80000000>; /* 2 GB */ 57*39a230aaSStefan Roese }; 58*39a230aaSStefan Roese 59*39a230aaSStefan Roese soc { 60*39a230aaSStefan Roese ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 61*39a230aaSStefan Roese MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; 62*39a230aaSStefan Roese 63*39a230aaSStefan Roese internal-regs { 64*39a230aaSStefan Roese spi@10600 { 65*39a230aaSStefan Roese pinctrl-names = "default"; 66*39a230aaSStefan Roese pinctrl-0 = <&spi0_pins>; 67*39a230aaSStefan Roese status = "okay"; 68*39a230aaSStefan Roese 69*39a230aaSStefan Roese spi-flash@0 { 70*39a230aaSStefan Roese #address-cells = <1>; 71*39a230aaSStefan Roese #size-cells = <1>; 72*39a230aaSStefan Roese compatible = "st,m25p128", "jedec,spi-nor"; 73*39a230aaSStefan Roese reg = <0>; /* Chip select 0 */ 74*39a230aaSStefan Roese spi-max-frequency = <50000000>; 75*39a230aaSStefan Roese m25p,fast-read; 76*39a230aaSStefan Roese }; 77*39a230aaSStefan Roese }; 78*39a230aaSStefan Roese 79*39a230aaSStefan Roese i2c@11000 { 80*39a230aaSStefan Roese pinctrl-names = "default"; 81*39a230aaSStefan Roese pinctrl-0 = <&i2c0_pins>; 82*39a230aaSStefan Roese status = "okay"; 83*39a230aaSStefan Roese clock-frequency = <100000>; 84*39a230aaSStefan Roese /* 85*39a230aaSStefan Roese * The EEPROM located at adresse 54 is needed 86*39a230aaSStefan Roese * for the boot - DO NOT ERASE IT - 87*39a230aaSStefan Roese */ 88*39a230aaSStefan Roese 89*39a230aaSStefan Roese expander0: pca9555@20 { 90*39a230aaSStefan Roese compatible = "nxp,pca9555"; 91*39a230aaSStefan Roese pinctrl-names = "default"; 92*39a230aaSStefan Roese pinctrl-0 = <&pca0_pins>; 93*39a230aaSStefan Roese interrupt-parent = <&gpio0>; 94*39a230aaSStefan Roese interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 95*39a230aaSStefan Roese gpio-controller; 96*39a230aaSStefan Roese #gpio-cells = <2>; 97*39a230aaSStefan Roese interrupt-controller; 98*39a230aaSStefan Roese #interrupt-cells = <2>; 99*39a230aaSStefan Roese reg = <0x20>; 100*39a230aaSStefan Roese }; 101*39a230aaSStefan Roese 102*39a230aaSStefan Roese expander1: pca9555@21 { 103*39a230aaSStefan Roese compatible = "nxp,pca9555"; 104*39a230aaSStefan Roese pinctrl-names = "default"; 105*39a230aaSStefan Roese interrupt-parent = <&gpio0>; 106*39a230aaSStefan Roese interrupts = <18 IRQ_TYPE_EDGE_FALLING>; 107*39a230aaSStefan Roese gpio-controller; 108*39a230aaSStefan Roese #gpio-cells = <2>; 109*39a230aaSStefan Roese interrupt-controller; 110*39a230aaSStefan Roese #interrupt-cells = <2>; 111*39a230aaSStefan Roese reg = <0x21>; 112*39a230aaSStefan Roese }; 113*39a230aaSStefan Roese 114*39a230aaSStefan Roese }; 115*39a230aaSStefan Roese 116*39a230aaSStefan Roese serial@12000 { 117*39a230aaSStefan Roese /* 118*39a230aaSStefan Roese * Exported on the micro USB connector CON16 119*39a230aaSStefan Roese * through an FTDI 120*39a230aaSStefan Roese */ 121*39a230aaSStefan Roese 122*39a230aaSStefan Roese pinctrl-names = "default"; 123*39a230aaSStefan Roese pinctrl-0 = <&uart0_pins>; 124*39a230aaSStefan Roese status = "okay"; 125*39a230aaSStefan Roese }; 126*39a230aaSStefan Roese 127*39a230aaSStefan Roese /* GE1 CON15 */ 128*39a230aaSStefan Roese ethernet@30000 { 129*39a230aaSStefan Roese pinctrl-names = "default"; 130*39a230aaSStefan Roese pinctrl-0 = <&ge1_rgmii_pins>; 131*39a230aaSStefan Roese status = "okay"; 132*39a230aaSStefan Roese phy = <&phy1>; 133*39a230aaSStefan Roese phy-mode = "rgmii-id"; 134*39a230aaSStefan Roese }; 135*39a230aaSStefan Roese 136*39a230aaSStefan Roese /* CON4 */ 137*39a230aaSStefan Roese usb@58000 { 138*39a230aaSStefan Roese vcc-supply = <®_usb2_0_vbus>; 139*39a230aaSStefan Roese status = "okay"; 140*39a230aaSStefan Roese }; 141*39a230aaSStefan Roese 142*39a230aaSStefan Roese /* GE0 CON1 */ 143*39a230aaSStefan Roese ethernet@70000 { 144*39a230aaSStefan Roese pinctrl-names = "default"; 145*39a230aaSStefan Roese /* 146*39a230aaSStefan Roese * The Reference Clock 0 is used to provide a 147*39a230aaSStefan Roese * clock to the PHY 148*39a230aaSStefan Roese */ 149*39a230aaSStefan Roese pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>; 150*39a230aaSStefan Roese status = "okay"; 151*39a230aaSStefan Roese phy = <&phy0>; 152*39a230aaSStefan Roese phy-mode = "rgmii-id"; 153*39a230aaSStefan Roese }; 154*39a230aaSStefan Roese 155*39a230aaSStefan Roese 156*39a230aaSStefan Roese mdio@72004 { 157*39a230aaSStefan Roese pinctrl-names = "default"; 158*39a230aaSStefan Roese pinctrl-0 = <&mdio_pins>; 159*39a230aaSStefan Roese 160*39a230aaSStefan Roese phy0: ethernet-phy@1 { 161*39a230aaSStefan Roese reg = <1>; 162*39a230aaSStefan Roese }; 163*39a230aaSStefan Roese 164*39a230aaSStefan Roese phy1: ethernet-phy@0 { 165*39a230aaSStefan Roese reg = <0>; 166*39a230aaSStefan Roese }; 167*39a230aaSStefan Roese }; 168*39a230aaSStefan Roese 169*39a230aaSStefan Roese sata@a8000 { 170*39a230aaSStefan Roese pinctrl-names = "default"; 171*39a230aaSStefan Roese pinctrl-0 = <&sata0_pins>, <&sata1_pins>; 172*39a230aaSStefan Roese status = "okay"; 173*39a230aaSStefan Roese #address-cells = <1>; 174*39a230aaSStefan Roese #size-cells = <0>; 175*39a230aaSStefan Roese 176*39a230aaSStefan Roese sata0: sata-port@0 { 177*39a230aaSStefan Roese reg = <0>; 178*39a230aaSStefan Roese target-supply = <®_5v_sata0>; 179*39a230aaSStefan Roese }; 180*39a230aaSStefan Roese 181*39a230aaSStefan Roese sata1: sata-port@1 { 182*39a230aaSStefan Roese reg = <1>; 183*39a230aaSStefan Roese target-supply = <®_5v_sata1>; 184*39a230aaSStefan Roese }; 185*39a230aaSStefan Roese }; 186*39a230aaSStefan Roese 187*39a230aaSStefan Roese sata@e0000 { 188*39a230aaSStefan Roese pinctrl-names = "default"; 189*39a230aaSStefan Roese pinctrl-0 = <&sata2_pins>, <&sata3_pins>; 190*39a230aaSStefan Roese status = "okay"; 191*39a230aaSStefan Roese #address-cells = <1>; 192*39a230aaSStefan Roese #size-cells = <0>; 193*39a230aaSStefan Roese 194*39a230aaSStefan Roese sata2: sata-port@0 { 195*39a230aaSStefan Roese reg = <0>; 196*39a230aaSStefan Roese target-supply = <®_5v_sata2>; 197*39a230aaSStefan Roese }; 198*39a230aaSStefan Roese 199*39a230aaSStefan Roese sata3: sata-port@1 { 200*39a230aaSStefan Roese reg = <1>; 201*39a230aaSStefan Roese target-supply = <®_5v_sata3>; 202*39a230aaSStefan Roese }; 203*39a230aaSStefan Roese }; 204*39a230aaSStefan Roese 205*39a230aaSStefan Roese sdhci@d8000 { 206*39a230aaSStefan Roese pinctrl-names = "default"; 207*39a230aaSStefan Roese pinctrl-0 = <&sdhci_pins>; 208*39a230aaSStefan Roese cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>; 209*39a230aaSStefan Roese no-1-8-v; 210*39a230aaSStefan Roese wp-inverted; 211*39a230aaSStefan Roese bus-width = <8>; 212*39a230aaSStefan Roese status = "okay"; 213*39a230aaSStefan Roese }; 214*39a230aaSStefan Roese 215*39a230aaSStefan Roese /* CON5 */ 216*39a230aaSStefan Roese usb3@f0000 { 217*39a230aaSStefan Roese vcc-supply = <®_usb2_1_vbus>; 218*39a230aaSStefan Roese status = "okay"; 219*39a230aaSStefan Roese }; 220*39a230aaSStefan Roese 221*39a230aaSStefan Roese /* CON7 */ 222*39a230aaSStefan Roese usb3@f8000 { 223*39a230aaSStefan Roese vcc-supply = <®_usb3_vbus>; 224*39a230aaSStefan Roese status = "okay"; 225*39a230aaSStefan Roese }; 226*39a230aaSStefan Roese }; 227*39a230aaSStefan Roese 228*39a230aaSStefan Roese pcie-controller { 229*39a230aaSStefan Roese status = "okay"; 230*39a230aaSStefan Roese /* 231*39a230aaSStefan Roese * One PCIe units is accessible through 232*39a230aaSStefan Roese * standard PCIe slot on the board. 233*39a230aaSStefan Roese */ 234*39a230aaSStefan Roese pcie@1,0 { 235*39a230aaSStefan Roese /* Port 0, Lane 0 */ 236*39a230aaSStefan Roese status = "okay"; 237*39a230aaSStefan Roese }; 238*39a230aaSStefan Roese 239*39a230aaSStefan Roese /* 240*39a230aaSStefan Roese * The two other PCIe units are accessible 241*39a230aaSStefan Roese * through mini PCIe slot on the board. 242*39a230aaSStefan Roese */ 243*39a230aaSStefan Roese pcie@2,0 { 244*39a230aaSStefan Roese /* Port 1, Lane 0 */ 245*39a230aaSStefan Roese status = "okay"; 246*39a230aaSStefan Roese }; 247*39a230aaSStefan Roese pcie@3,0 { 248*39a230aaSStefan Roese /* Port 2, Lane 0 */ 249*39a230aaSStefan Roese status = "okay"; 250*39a230aaSStefan Roese }; 251*39a230aaSStefan Roese }; 252*39a230aaSStefan Roese 253*39a230aaSStefan Roese gpio-fan { 254*39a230aaSStefan Roese compatible = "gpio-fan"; 255*39a230aaSStefan Roese gpios = <&expander1 3 GPIO_ACTIVE_HIGH>; 256*39a230aaSStefan Roese gpio-fan,speed-map = < 0 0 257*39a230aaSStefan Roese 3000 1>; 258*39a230aaSStefan Roese }; 259*39a230aaSStefan Roese }; 260*39a230aaSStefan Roese 261*39a230aaSStefan Roese reg_usb3_vbus: usb3-vbus { 262*39a230aaSStefan Roese compatible = "regulator-fixed"; 263*39a230aaSStefan Roese regulator-name = "usb3-vbus"; 264*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 265*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 266*39a230aaSStefan Roese enable-active-high; 267*39a230aaSStefan Roese regulator-always-on; 268*39a230aaSStefan Roese gpio = <&expander1 15 GPIO_ACTIVE_HIGH>; 269*39a230aaSStefan Roese }; 270*39a230aaSStefan Roese 271*39a230aaSStefan Roese reg_usb2_0_vbus: v5-vbus0 { 272*39a230aaSStefan Roese compatible = "regulator-fixed"; 273*39a230aaSStefan Roese regulator-name = "v5.0-vbus0"; 274*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 275*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 276*39a230aaSStefan Roese enable-active-high; 277*39a230aaSStefan Roese regulator-always-on; 278*39a230aaSStefan Roese gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; 279*39a230aaSStefan Roese }; 280*39a230aaSStefan Roese 281*39a230aaSStefan Roese reg_usb2_1_vbus: v5-vbus1 { 282*39a230aaSStefan Roese compatible = "regulator-fixed"; 283*39a230aaSStefan Roese regulator-name = "v5.0-vbus1"; 284*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 285*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 286*39a230aaSStefan Roese enable-active-high; 287*39a230aaSStefan Roese regulator-always-on; 288*39a230aaSStefan Roese gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; 289*39a230aaSStefan Roese }; 290*39a230aaSStefan Roese 291*39a230aaSStefan Roese reg_usb2_1_vbus: v5-vbus1 { 292*39a230aaSStefan Roese compatible = "regulator-fixed"; 293*39a230aaSStefan Roese regulator-name = "v5.0-vbus1"; 294*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 295*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 296*39a230aaSStefan Roese enable-active-high; 297*39a230aaSStefan Roese regulator-always-on; 298*39a230aaSStefan Roese gpio = <&expander0 4 GPIO_ACTIVE_HIGH>; 299*39a230aaSStefan Roese }; 300*39a230aaSStefan Roese 301*39a230aaSStefan Roese reg_sata0: pwr-sata0 { 302*39a230aaSStefan Roese compatible = "regulator-fixed"; 303*39a230aaSStefan Roese regulator-name = "pwr_en_sata0"; 304*39a230aaSStefan Roese enable-active-high; 305*39a230aaSStefan Roese regulator-always-on; 306*39a230aaSStefan Roese 307*39a230aaSStefan Roese }; 308*39a230aaSStefan Roese 309*39a230aaSStefan Roese reg_5v_sata0: v5-sata0 { 310*39a230aaSStefan Roese compatible = "regulator-fixed"; 311*39a230aaSStefan Roese regulator-name = "v5.0-sata0"; 312*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 313*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 314*39a230aaSStefan Roese regulator-always-on; 315*39a230aaSStefan Roese vin-supply = <®_sata0>; 316*39a230aaSStefan Roese }; 317*39a230aaSStefan Roese 318*39a230aaSStefan Roese reg_12v_sata0: v12-sata0 { 319*39a230aaSStefan Roese compatible = "regulator-fixed"; 320*39a230aaSStefan Roese regulator-name = "v12.0-sata0"; 321*39a230aaSStefan Roese regulator-min-microvolt = <12000000>; 322*39a230aaSStefan Roese regulator-max-microvolt = <12000000>; 323*39a230aaSStefan Roese regulator-always-on; 324*39a230aaSStefan Roese vin-supply = <®_sata0>; 325*39a230aaSStefan Roese }; 326*39a230aaSStefan Roese 327*39a230aaSStefan Roese reg_sata1: pwr-sata1 { 328*39a230aaSStefan Roese regulator-name = "pwr_en_sata1"; 329*39a230aaSStefan Roese compatible = "regulator-fixed"; 330*39a230aaSStefan Roese regulator-min-microvolt = <12000000>; 331*39a230aaSStefan Roese regulator-max-microvolt = <12000000>; 332*39a230aaSStefan Roese enable-active-high; 333*39a230aaSStefan Roese regulator-always-on; 334*39a230aaSStefan Roese gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 335*39a230aaSStefan Roese }; 336*39a230aaSStefan Roese 337*39a230aaSStefan Roese reg_5v_sata1: v5-sata1 { 338*39a230aaSStefan Roese compatible = "regulator-fixed"; 339*39a230aaSStefan Roese regulator-name = "v5.0-sata1"; 340*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 341*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 342*39a230aaSStefan Roese regulator-always-on; 343*39a230aaSStefan Roese vin-supply = <®_sata1>; 344*39a230aaSStefan Roese }; 345*39a230aaSStefan Roese 346*39a230aaSStefan Roese reg_12v_sata1: v12-sata1 { 347*39a230aaSStefan Roese compatible = "regulator-fixed"; 348*39a230aaSStefan Roese regulator-name = "v12.0-sata1"; 349*39a230aaSStefan Roese regulator-min-microvolt = <12000000>; 350*39a230aaSStefan Roese regulator-max-microvolt = <12000000>; 351*39a230aaSStefan Roese regulator-always-on; 352*39a230aaSStefan Roese vin-supply = <®_sata1>; 353*39a230aaSStefan Roese }; 354*39a230aaSStefan Roese 355*39a230aaSStefan Roese reg_sata2: pwr-sata2 { 356*39a230aaSStefan Roese compatible = "regulator-fixed"; 357*39a230aaSStefan Roese regulator-name = "pwr_en_sata2"; 358*39a230aaSStefan Roese enable-active-high; 359*39a230aaSStefan Roese regulator-always-on; 360*39a230aaSStefan Roese gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; 361*39a230aaSStefan Roese }; 362*39a230aaSStefan Roese 363*39a230aaSStefan Roese reg_5v_sata2: v5-sata2 { 364*39a230aaSStefan Roese compatible = "regulator-fixed"; 365*39a230aaSStefan Roese regulator-name = "v5.0-sata2"; 366*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 367*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 368*39a230aaSStefan Roese regulator-always-on; 369*39a230aaSStefan Roese vin-supply = <®_sata2>; 370*39a230aaSStefan Roese }; 371*39a230aaSStefan Roese 372*39a230aaSStefan Roese reg_12v_sata2: v12-sata2 { 373*39a230aaSStefan Roese compatible = "regulator-fixed"; 374*39a230aaSStefan Roese regulator-name = "v12.0-sata2"; 375*39a230aaSStefan Roese regulator-min-microvolt = <12000000>; 376*39a230aaSStefan Roese regulator-max-microvolt = <12000000>; 377*39a230aaSStefan Roese regulator-always-on; 378*39a230aaSStefan Roese vin-supply = <®_sata2>; 379*39a230aaSStefan Roese }; 380*39a230aaSStefan Roese 381*39a230aaSStefan Roese reg_sata3: pwr-sata3 { 382*39a230aaSStefan Roese compatible = "regulator-fixed"; 383*39a230aaSStefan Roese regulator-name = "pwr_en_sata3"; 384*39a230aaSStefan Roese enable-active-high; 385*39a230aaSStefan Roese regulator-always-on; 386*39a230aaSStefan Roese gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; 387*39a230aaSStefan Roese }; 388*39a230aaSStefan Roese 389*39a230aaSStefan Roese reg_5v_sata3: v5-sata3 { 390*39a230aaSStefan Roese compatible = "regulator-fixed"; 391*39a230aaSStefan Roese regulator-name = "v5.0-sata3"; 392*39a230aaSStefan Roese regulator-min-microvolt = <5000000>; 393*39a230aaSStefan Roese regulator-max-microvolt = <5000000>; 394*39a230aaSStefan Roese regulator-always-on; 395*39a230aaSStefan Roese vin-supply = <®_sata3>; 396*39a230aaSStefan Roese }; 397*39a230aaSStefan Roese 398*39a230aaSStefan Roese reg_12v_sata3: v12-sata3 { 399*39a230aaSStefan Roese compatible = "regulator-fixed"; 400*39a230aaSStefan Roese regulator-name = "v12.0-sata3"; 401*39a230aaSStefan Roese regulator-min-microvolt = <12000000>; 402*39a230aaSStefan Roese regulator-max-microvolt = <12000000>; 403*39a230aaSStefan Roese regulator-always-on; 404*39a230aaSStefan Roese vin-supply = <®_sata3>; 405*39a230aaSStefan Roese }; 406*39a230aaSStefan Roese}; 407*39a230aaSStefan Roese 408*39a230aaSStefan Roese&pinctrl { 409*39a230aaSStefan Roese pca0_pins: pca0_pins { 410*39a230aaSStefan Roese marvell,pins = "mpp18"; 411*39a230aaSStefan Roese marvell,function = "gpio"; 412*39a230aaSStefan Roese }; 413*39a230aaSStefan Roese}; 414