1/*
2 * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
3 *
4 *  Copyright (C) 2015 Russell King
5 *
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board.  Things will change, don't expect this file to
9 * remain compatible info the future.
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 *  a) This file is free software; you can redistribute it and/or
17 *     modify it under the terms of the GNU General Public License
18 *     version 2 as published by the Free Software Foundation.
19 *
20 *     This file is distributed in the hope that it will be useful
21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 *     GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include <dt-bindings/input/input.h>
51#include <dt-bindings/gpio/gpio.h>
52#include "armada-388.dtsi"
53
54/ {
55	model = "SolidRun Clearfog A1";
56	compatible = "solidrun,clearfog-a1", "marvell,armada388",
57		"marvell,armada385", "marvell,armada380";
58
59	aliases {
60		/* So that mvebu u-boot can update the MAC addresses */
61		ethernet1 = &eth0;
62		ethernet2 = &eth1;
63		ethernet3 = &eth2;
64		spi1 = &spi1;
65	};
66
67	chosen {
68		stdout-path = "serial0:115200n8";
69	};
70
71	memory {
72		device_type = "memory";
73		reg = <0x00000000 0x10000000>; /* 256 MB */
74	};
75
76	reg_3p3v: regulator-3p3v {
77		compatible = "regulator-fixed";
78		regulator-name = "3P3V";
79		regulator-min-microvolt = <3300000>;
80		regulator-max-microvolt = <3300000>;
81		regulator-always-on;
82	};
83
84	soc {
85		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
86			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
87			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
88			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
89
90		internal-regs {
91			ethernet@30000 {
92				mac-address = [00 50 43 02 02 02];
93				phy-mode = "sgmii";
94				status = "okay";
95
96				fixed-link {
97					speed = <1000>;
98					full-duplex;
99				};
100			};
101
102			ethernet@34000 {
103				mac-address = [00 50 43 02 02 03];
104				managed = "in-band-status";
105				phy-mode = "sgmii";
106				status = "okay";
107			};
108
109			ethernet@70000 {
110				mac-address = [00 50 43 02 02 01];
111				pinctrl-0 = <&ge0_rgmii_pins>;
112				pinctrl-names = "default";
113				phy = <&phy_dedicated>;
114				phy-mode = "rgmii-id";
115				status = "okay";
116			};
117
118			i2c@11000 {
119				/* Is there anything on this? */
120				clock-frequency = <100000>;
121				pinctrl-0 = <&i2c0_pins>;
122				pinctrl-names = "default";
123				status = "okay";
124
125				/*
126				 * PCA9655 GPIO expander, up to 1MHz clock.
127				 *  0-CON3 CLKREQ#
128				 *  1-CON3 PERST#
129				 *  2-CON2 PERST#
130				 *  3-CON3 W_DISABLE
131				 *  4-CON2 CLKREQ#
132				 *  5-USB3 overcurrent
133				 *  6-USB3 power
134				 *  7-CON2 W_DISABLE
135				 *  8-JP4 P1
136				 *  9-JP4 P4
137				 * 10-JP4 P5
138				 * 11-m.2 DEVSLP
139				 * 12-SFP_LOS
140				 * 13-SFP_TX_FAULT
141				 * 14-SFP_TX_DISABLE
142				 * 15-SFP_MOD_DEF0
143				 */
144				expander0: gpio-expander@20 {
145					/*
146					 * This is how it should be:
147					 * compatible = "onnn,pca9655",
148					 *	 "nxp,pca9555";
149					 * but you can't do this because of
150					 * the way I2C works.
151					 */
152					compatible = "nxp,pca9555";
153					gpio-controller;
154					#gpio-cells = <2>;
155					reg = <0x20>;
156
157					pcie1_0_clkreq {
158						gpio-hog;
159						gpios = <0 GPIO_ACTIVE_LOW>;
160						input;
161						line-name = "pcie1.0-clkreq";
162					};
163					pcie1_0_w_disable {
164						gpio-hog;
165						gpios = <3 GPIO_ACTIVE_LOW>;
166						output-low;
167						line-name = "pcie1.0-w-disable";
168					};
169					pcie2_0_clkreq {
170						gpio-hog;
171						gpios = <4 GPIO_ACTIVE_LOW>;
172						input;
173						line-name = "pcie2.0-clkreq";
174					};
175					pcie2_0_w_disable {
176						gpio-hog;
177						gpios = <7 GPIO_ACTIVE_LOW>;
178						output-low;
179						line-name = "pcie2.0-w-disable";
180					};
181					usb3_ilimit {
182						gpio-hog;
183						gpios = <5 GPIO_ACTIVE_LOW>;
184						input;
185						line-name = "usb3-current-limit";
186					};
187					usb3_power {
188						gpio-hog;
189						gpios = <6 GPIO_ACTIVE_HIGH>;
190						output-high;
191						line-name = "usb3-power";
192					};
193					m2_devslp {
194						gpio-hog;
195						gpios = <11 GPIO_ACTIVE_HIGH>;
196						output-low;
197						line-name = "m.2 devslp";
198					};
199				};
200
201				/* The MCP3021 is 100kHz clock only */
202				mikrobus_adc: mcp3021@4c {
203					compatible = "microchip,mcp3021";
204					reg = <0x4c>;
205				};
206
207				/* Also something at 0x64 */
208			};
209
210			i2c@11100 {
211				/*
212				 * Routed to SFP, mikrobus, and PCIe.
213				 * SFP limits this to 100kHz, and requires
214				 *  an AT24C01A/02/04 with address pins tied
215				 *  low, which takes addresses 0x50 and 0x51.
216				 * Mikrobus doesn't specify beyond an I2C
217				 *  bus being present.
218				 * PCIe uses ARP to assign addresses, or
219				 *  0x63-0x64.
220				 */
221				clock-frequency = <100000>;
222				pinctrl-0 = <&clearfog_i2c1_pins>;
223				pinctrl-names = "default";
224				status = "okay";
225			};
226
227			mdio@72004 {
228				pinctrl-0 = <&mdio_pins>;
229				pinctrl-names = "default";
230
231				phy_dedicated: ethernet-phy@0 {
232					/*
233					 * Annoyingly, the marvell phy driver
234					 * configures the LED register, rather
235					 * than preserving reset-loaded setting.
236					 * We undo that rubbish here.
237					 */
238					marvell,reg-init = <3 16 0 0x101e>;
239					reg = <0>;
240				};
241			};
242
243			pinctrl@18000 {
244				clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
245					marvell,pins = "mpp46";
246					marvell,function = "ref";
247				};
248				clearfog_dsa0_pins: clearfog-dsa0-pins {
249					marvell,pins = "mpp23", "mpp41";
250					marvell,function = "gpio";
251				};
252				clearfog_i2c1_pins: i2c1-pins {
253					/* SFP, PCIe, mSATA, mikrobus */
254					marvell,pins = "mpp26", "mpp27";
255					marvell,function = "i2c1";
256				};
257				clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
258					marvell,pins = "mpp20";
259					marvell,function = "gpio";
260				};
261				clearfog_sdhci_pins: clearfog-sdhci-pins {
262					marvell,pins = "mpp21", "mpp28",
263						       "mpp37", "mpp38",
264						       "mpp39", "mpp40";
265					marvell,function = "sd0";
266				};
267				clearfog_spi1_cs_pins: spi1-cs-pins {
268					marvell,pins = "mpp55";
269					marvell,function = "spi1";
270				};
271				mikro_pins: mikro-pins {
272					/* int: mpp22 rst: mpp29 */
273					marvell,pins = "mpp22", "mpp29";
274					marvell,function = "gpio";
275				};
276				mikro_spi_pins: mikro-spi-pins {
277					marvell,pins = "mpp43";
278					marvell,function = "spi1";
279				};
280				mikro_uart_pins: mikro-uart-pins {
281					marvell,pins = "mpp24", "mpp25";
282					marvell,function = "ua1";
283				};
284				rear_button_pins: rear-button-pins {
285					marvell,pins = "mpp34";
286					marvell,function = "gpio";
287				};
288			};
289
290			rtc@a3800 {
291				/*
292				 * If the rtc doesn't work, run "date reset"
293				 * twice in u-boot.
294				 */
295				status = "okay";
296			};
297
298			sata@a8000 {
299				/* pinctrl? */
300				status = "okay";
301			};
302
303			sata@e0000 {
304				/* pinctrl? */
305				status = "okay";
306			};
307
308			sdhci@d8000 {
309				bus-width = <4>;
310				cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
311				no-1-8-v;
312				pinctrl-0 = <&clearfog_sdhci_pins
313					     &clearfog_sdhci_cd_pins>;
314				pinctrl-names = "default";
315				status = "okay";
316				vmmc = <&reg_3p3v>;
317				wp-inverted;
318			};
319
320			serial@12000 {
321				pinctrl-0 = <&uart0_pins>;
322				pinctrl-names = "default";
323				status = "okay";
324				u-boot,dm-pre-reloc;
325			};
326
327			serial@12100 {
328				/* mikrobus uart */
329				pinctrl-0 = <&mikro_uart_pins>;
330				pinctrl-names = "default";
331				status = "okay";
332			};
333
334			spi1: spi@10680 {
335				/*
336				 * CS0: W25Q32
337				 * CS1:
338				 * CS2: mikrobus
339				 */
340				pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
341				pinctrl-names = "default";
342				status = "okay";
343
344				spi-flash@0 {
345					#address-cells = <1>;
346					#size-cells = <0>;
347					compatible = "w25q32", "jedec,spi-nor", "spi-flash";
348					reg = <0>; /* Chip select 0 */
349					spi-max-frequency = <3000000>;
350				};
351			};
352
353			usb3@f8000 {
354				status = "okay";
355			};
356		};
357
358		pcie-controller {
359			status = "okay";
360			/*
361			 * The two PCIe units are accessible through
362			 * the mini-PCIe connectors on the board.
363			 */
364			pcie@2,0 {
365				/* Port 1, Lane 0. CONN3, nearest power. */
366				reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
367				status = "okay";
368			};
369			pcie@3,0 {
370				/* Port 2, Lane 0. CONN2, nearest CPU. */
371				reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
372				status = "okay";
373			};
374		};
375	};
376
377	sfp: sfp {
378		compatible = "sff,sfp";
379		i2c-bus = <&i2c1>;
380		los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
381		moddef0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
382		sfp,ethernet = <&eth2>;
383		tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
384		tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
385	};
386
387	dsa@0 {
388		compatible = "marvell,dsa";
389		dsa,ethernet = <&eth1>;
390		dsa,mii-bus = <&mdio>;
391		pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
392		pinctrl-names = "default";
393		#address-cells = <2>;
394		#size-cells = <0>;
395
396		switch@0 {
397			#address-cells = <1>;
398			#size-cells = <0>;
399			reg = <4 0>;
400
401			port@0 {
402				reg = <0>;
403				label = "lan1";
404			};
405
406			port@1 {
407				reg = <1>;
408				label = "lan2";
409			};
410
411			port@2 {
412				reg = <2>;
413				label = "lan3";
414			};
415
416			port@3 {
417				reg = <3>;
418				label = "lan4";
419			};
420
421			port@4 {
422				reg = <4>;
423				label = "lan5";
424			};
425
426			port@5 {
427				reg = <5>;
428				label = "cpu";
429			};
430
431			port@6 {
432				/* 88E1512 external phy */
433				reg = <6>;
434				label = "lan6";
435				fixed-link {
436					speed = <1000>;
437					full-duplex;
438				};
439			};
440		};
441	};
442
443	gpio-keys {
444		compatible = "gpio-keys";
445		pinctrl-0 = <&rear_button_pins>;
446		pinctrl-names = "default";
447
448		button_0 {
449			/* The rear SW3 button */
450			label = "Rear Button";
451			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
452			linux,can-disable;
453			linux,code = <BTN_0>;
454		};
455	};
456};
457
458/*
459+#define A38x_CUSTOMER_BOARD_1_MPP16_23         0x00400011
460MPP18: gpio		? (pca9655 int?)
461MPP19: gpio		? (clkreq?)
462MPP20: gpio		? (sd0 detect)
463MPP21: sd0:cmd		x sd0
464MPP22: gpio		x mikro int
465MPP23: gpio		x switch irq
466+#define A38x_CUSTOMER_BOARD_1_MPP24_31         0x22043333
467MPP24: ua1:rxd		x mikro rx
468MPP25: ua1:txd		x mikro tx
469MPP26: i2c1:sck		x mikro sck
470MPP27: i2c1:sda		x mikro sda
471MPP28: sd0:clk		x sd0
472MPP29: gpio		x mikro rst
473MPP30: ge1:txd2		? (config)
474MPP31: ge1:txd3		? (config)
475+#define A38x_CUSTOMER_BOARD_1_MPP32_39         0x44400002
476MPP32: ge1:txctl	? (unused)
477MPP33: gpio		? (pic_com0)
478MPP34: gpio		x rear button (pic_com1)
479MPP35: gpio		? (pic_com2)
480MPP36: gpio		? (unused)
481MPP37: sd0:d3		x sd0
482MPP38: sd0:d0		x sd0
483MPP39: sd0:d1		x sd0
484+#define A38x_CUSTOMER_BOARD_1_MPP40_47         0x41144004
485MPP40: sd0:d2		x sd0
486MPP41: gpio		x switch reset
487MPP42: gpio		? sw1-1
488MPP43: spi1:cs2		x mikro cs
489MPP44: sata3:prsnt	? (unused)
490MPP45: ref:clk_out0	?
491MPP46: ref:clk_out1	x switch clk
492MPP47: 4		? (unused)
493+#define A38x_CUSTOMER_BOARD_1_MPP48_55         0x40333333
494MPP48: tdm:pclk
495MPP49: tdm:fsync
496MPP50: tdm:drx
497MPP51: tdm:dtx
498MPP52: tdm:int
499MPP53: tdm:rst
500MPP54: gpio		? (pwm)
501MPP55: spi1:cs1		x slic
502+#define A38x_CUSTOMER_BOARD_1_MPP56_63         0x00004444
503MPP56: spi1:mosi	x mikro mosi
504MPP57: spi1:sck		x mikro sck
505MPP58: spi1:miso	x mikro miso
506MPP59: spi1:cs0		x w25q32
507*/
508