1/*
2 * Device Tree file for SolidRun Clearfog revision A1 rev 2.0 (88F6828)
3 *
4 *  Copyright (C) 2015 Russell King
5 *
6 * This board is in development; the contents of this file work with
7 * the A1 rev 2.0 of the board, which does not represent final
8 * production board.  Things will change, don't expect this file to
9 * remain compatible info the future.
10 *
11 * This file is dual-licensed: you can use it either under the terms
12 * of the GPL or the X11 license, at your option. Note that this dual
13 * licensing only applies to this file, and not this project as a
14 * whole.
15 *
16 *  a) This file is free software; you can redistribute it and/or
17 *     modify it under the terms of the GNU General Public License
18 *     version 2 as published by the Free Software Foundation.
19 *
20 *     This file is distributed in the hope that it will be useful
21 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23 *     GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 *  b) Permission is hereby granted, free of charge, to any person
28 *     obtaining a copy of this software and associated documentation
29 *     files (the "Software"), to deal in the Software without
30 *     restriction, including without limitation the rights to use
31 *     copy, modify, merge, publish, distribute, sublicense, and/or
32 *     sell copies of the Software, and to permit persons to whom the
33 *     Software is furnished to do so, subject to the following
34 *     conditions:
35 *
36 *     The above copyright notice and this permission notice shall be
37 *     included in all copies or substantial portions of the Software.
38 *
39 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 *     OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49/dts-v1/;
50#include <dt-bindings/input/input.h>
51#include <dt-bindings/gpio/gpio.h>
52#include "armada-388.dtsi"
53#include "armada-38x-solidrun-microsom.dtsi"
54
55/ {
56	model = "SolidRun Clearfog A1";
57	compatible = "solidrun,clearfog-a1", "marvell,armada388",
58		"marvell,armada385", "marvell,armada380";
59
60	aliases {
61		/* So that mvebu u-boot can update the MAC addresses */
62		ethernet1 = &eth0;
63		ethernet2 = &eth1;
64		ethernet3 = &eth2;
65		spi1 = &spi1;
66		i2c0 = &i2c0;
67		i2c1 = &i2c1;
68	};
69
70	chosen {
71		stdout-path = "serial0:115200n8";
72	};
73
74	reg_3p3v: regulator-3p3v {
75		compatible = "regulator-fixed";
76		regulator-name = "3P3V";
77		regulator-min-microvolt = <3300000>;
78		regulator-max-microvolt = <3300000>;
79		regulator-always-on;
80	};
81
82	soc {
83		internal-regs {
84			rtc@a3800 {
85				/*
86				 * If the rtc doesn't work, run "date reset"
87				 * twice in u-boot.
88				 */
89				status = "okay";
90			};
91
92			sata@a8000 {
93				/* pinctrl? */
94				status = "okay";
95			};
96
97			sata@e0000 {
98				/* pinctrl? */
99				status = "okay";
100			};
101
102			sdhci@d8000 {
103				bus-width = <4>;
104				cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
105				no-1-8-v;
106				pinctrl-0 = <&microsom_sdhci_pins
107					     &clearfog_sdhci_cd_pins>;
108				pinctrl-names = "default";
109				status = "okay";
110				vmmc = <&reg_3p3v>;
111				wp-inverted;
112			};
113
114			serial@12100 {
115				/* mikrobus uart */
116				pinctrl-0 = <&mikro_uart_pins>;
117				pinctrl-names = "default";
118				status = "okay";
119			};
120
121			spi1: spi@10680 {
122				/*
123				 * CS0: W25Q32
124				 * CS1:
125				 * CS2: mikrobus
126				 */
127				pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
128				pinctrl-names = "default";
129				status = "okay";
130			};
131
132			usb0: usb3@f8000 {
133				/* CON7, USB-A port on back of device */
134				status = "okay";
135			};
136		};
137
138		pcie-controller {
139			status = "okay";
140			/*
141			 * The two PCIe units are accessible through
142			 * the mini-PCIe connectors on the board.
143			 */
144			pcie@2,0 {
145				/* Port 1, Lane 0. CONN3, nearest power. */
146				reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
147				status = "okay";
148			};
149			pcie@3,0 {
150				/* Port 2, Lane 0. CONN2, nearest CPU. */
151				reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
152				status = "okay";
153			};
154		};
155	};
156
157	gpio-keys {
158		compatible = "gpio-keys";
159		pinctrl-0 = <&rear_button_pins>;
160		pinctrl-names = "default";
161
162		button_0 {
163			/* The rear SW3 button */
164			label = "Rear Button";
165			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
166			linux,can-disable;
167			linux,code = <BTN_0>;
168		};
169	};
170};
171
172&w25q32 {
173	status = "okay";
174};
175
176&eth1 {
177	managed = "in-band-status";
178	phy-mode = "sgmii";
179	status = "okay";
180};
181
182&eth2 {
183	phy-mode = "sgmii";
184	status = "okay";
185};
186
187&i2c0 {
188	clock-frequency = <400000>;
189	pinctrl-0 = <&i2c0_pins>;
190	pinctrl-names = "default";
191	status = "okay";
192
193	/*
194	 * PCA9655 GPIO expander, up to 1MHz clock.
195	 *  0-CON3 CLKREQ#
196	 *  1-CON3 PERST#
197	 *  2-CON2 PERST#
198	 *  3-CON3 W_DISABLE
199	 *  4-CON2 CLKREQ#
200	 *  5-USB3 overcurrent
201	 *  6-USB3 power
202	 *  7-CON2 W_DISABLE
203	 *  8-JP4 P1
204	 *  9-JP4 P4
205	 * 10-JP4 P5
206	 * 11-m.2 DEVSLP
207	 * 12-SFP_LOS
208	 * 13-SFP_TX_FAULT
209	 * 14-SFP_TX_DISABLE
210	 * 15-SFP_MOD_DEF0
211	 */
212	expander0: gpio-expander@20 {
213		/*
214		 * This is how it should be:
215		 * compatible = "onnn,pca9655",
216		 *	 "nxp,pca9555";
217		 * but you can't do this because of
218		 * the way I2C works.
219		 */
220		compatible = "nxp,pca9555";
221		gpio-controller;
222		#gpio-cells = <2>;
223		reg = <0x20>;
224
225		pcie1_0_clkreq {
226			gpio-hog;
227			gpios = <0 GPIO_ACTIVE_LOW>;
228			input;
229			line-name = "pcie1.0-clkreq";
230		};
231		pcie1_0_w_disable {
232			gpio-hog;
233			gpios = <3 GPIO_ACTIVE_LOW>;
234			output-low;
235			line-name = "pcie1.0-w-disable";
236		};
237		pcie2_0_clkreq {
238			gpio-hog;
239			gpios = <4 GPIO_ACTIVE_LOW>;
240			input;
241			line-name = "pcie2.0-clkreq";
242		};
243		pcie2_0_w_disable {
244			gpio-hog;
245			gpios = <7 GPIO_ACTIVE_LOW>;
246			output-low;
247			line-name = "pcie2.0-w-disable";
248		};
249		usb3_ilimit {
250			gpio-hog;
251			gpios = <5 GPIO_ACTIVE_LOW>;
252			input;
253			line-name = "usb3-current-limit";
254		};
255		usb3_power {
256			gpio-hog;
257			gpios = <6 GPIO_ACTIVE_HIGH>;
258			output-high;
259			line-name = "usb3-power";
260		};
261		m2_devslp {
262			gpio-hog;
263			gpios = <11 GPIO_ACTIVE_HIGH>;
264			output-low;
265			line-name = "m.2 devslp";
266		};
267	};
268
269	mikrobus_adc: mcp3021@4c {
270		compatible = "microchip,mcp3021";
271		reg = <0x4c>;
272	};
273};
274
275&i2c1 {
276	/*
277	 * Routed to SFP, mikrobus, and PCIe.
278	 * SFP limits this to 100kHz, and requires
279	 *  an AT24C01A/02/04 with address pins tied
280	 *  low, which takes addresses 0x50 and 0x51.
281	 * Mikrobus doesn't specify beyond an I2C
282	 *  bus being present.
283	 * PCIe uses ARP to assign addresses, or
284	 *  0x63-0x64.
285	 */
286	clock-frequency = <100000>;
287	pinctrl-0 = <&clearfog_i2c1_pins>;
288	pinctrl-names = "default";
289	status = "okay";
290};
291
292&pinctrl {
293	clearfog_i2c1_pins: i2c1-pins {
294		/* SFP, PCIe, mSATA, mikrobus */
295		marvell,pins = "mpp26", "mpp27";
296		marvell,function = "i2c1";
297	};
298	clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
299		marvell,pins = "mpp20";
300		marvell,function = "gpio";
301	};
302	clearfog_spi1_cs_pins: spi1-cs-pins {
303		marvell,pins = "mpp55";
304		marvell,function = "spi1";
305	};
306	mikro_pins: mikro-pins {
307		/* int: mpp22 rst: mpp29 */
308		marvell,pins = "mpp22", "mpp29";
309		marvell,function = "gpio";
310	};
311	mikro_spi_pins: mikro-spi-pins {
312		marvell,pins = "mpp43";
313		marvell,function = "spi1";
314	};
315	mikro_uart_pins: mikro-uart-pins {
316		marvell,pins = "mpp24", "mpp25";
317		marvell,function = "ua1";
318	};
319	rear_button_pins: rear-button-pins {
320		marvell,pins = "mpp34";
321		marvell,function = "gpio";
322	};
323};
324
325/*
326+#define A38x_CUSTOMER_BOARD_1_MPP16_23         0x00400011
327MPP18: gpio		? (pca9655 int?)
328MPP19: gpio		? (clkreq?)
329MPP20: gpio		? (sd0 detect)
330MPP21: sd0:cmd		x sd0
331MPP22: gpio		x mikro int
332MPP23: gpio		x switch irq
333+#define A38x_CUSTOMER_BOARD_1_MPP24_31         0x22043333
334MPP24: ua1:rxd		x mikro rx
335MPP25: ua1:txd		x mikro tx
336MPP26: i2c1:sck		x mikro sck
337MPP27: i2c1:sda		x mikro sda
338MPP28: sd0:clk		x sd0
339MPP29: gpio		x mikro rst
340MPP30: ge1:txd2		? (config)
341MPP31: ge1:txd3		? (config)
342+#define A38x_CUSTOMER_BOARD_1_MPP32_39         0x44400002
343MPP32: ge1:txctl	? (unused)
344MPP33: gpio		? (pic_com0)
345MPP34: gpio		x rear button (pic_com1)
346MPP35: gpio		? (pic_com2)
347MPP36: gpio		? (unused)
348MPP37: sd0:d3		x sd0
349MPP38: sd0:d0		x sd0
350MPP39: sd0:d1		x sd0
351+#define A38x_CUSTOMER_BOARD_1_MPP40_47         0x41144004
352MPP40: sd0:d2		x sd0
353MPP41: gpio		x switch reset
354MPP42: gpio		? sw1-1
355MPP43: spi1:cs2		x mikro cs
356MPP44: sata3:prsnt	? (unused)
357MPP45: ref:clk_out0	?
358MPP46: ref:clk_out1	x switch clk
359MPP47: 4		? (unused)
360+#define A38x_CUSTOMER_BOARD_1_MPP48_55         0x40333333
361MPP48: tdm:pclk
362MPP49: tdm:fsync
363MPP50: tdm:drx
364MPP51: tdm:dtx
365MPP52: tdm:int
366MPP53: tdm:rst
367MPP54: gpio		? (pwm)
368MPP55: spi1:cs1		x slic
369+#define A38x_CUSTOMER_BOARD_1_MPP56_63         0x00004444
370MPP56: spi1:mosi	x mikro mosi
371MPP57: spi1:sck		x mikro sck
372MPP58: spi1:miso	x mikro miso
373MPP59: spi1:cs0		x w25q32
374*/
375