xref: /openbmc/u-boot/arch/arm/dts/armada-380.dtsi (revision 552a848e)
1 /*
2  * Device Tree Include file for Marvell Armada 380 SoC.
3  *
4  * Copyright (C) 2014 Marvell
5  *
6  * Lior Amsalem <alior@marvell.com>
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9  *
10  * This file is dual-licensed: you can use it either under the terms
11  * of the GPL or the X11 license, at your option. Note that this dual
12  * licensing only applies to this file, and not this project as a
13  * whole.
14  *
15  *  a) This file is free software; you can redistribute it and/or
16  *     modify it under the terms of the GNU General Public License as
17  *     published by the Free Software Foundation; either version 2 of the
18  *     License, or (at your option) any later version.
19  *
20  *     This file is distributed in the hope that it will be useful
21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  *     GNU General Public License for more details.
24  *
25  * Or, alternatively
26  *
27  *  b) Permission is hereby granted, free of charge, to any person
28  *     obtaining a copy of this software and associated documentation
29  *     files (the "Software"), to deal in the Software without
30  *     restriction, including without limitation the rights to use
31  *     copy, modify, merge, publish, distribute, sublicense, and/or
32  *     sell copies of the Software, and to permit persons to whom the
33  *     Software is furnished to do so, subject to the following
34  *     conditions:
35  *
36  *     The above copyright notice and this permission notice shall be
37  *     included in all copies or substantial portions of the Software.
38  *
39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46  *     OTHER DEALINGS IN THE SOFTWARE.
47  */
48 
49 #include "armada-38x.dtsi"
50 
51 / {
52 	model = "Marvell Armada 380 family SoC";
53 	compatible = "marvell,armada380";
54 
55 	cpus {
56 		#address-cells = <1>;
57 		#size-cells = <0>;
58 		enable-method = "marvell,armada-380-smp";
59 
60 		cpu@0 {
61 			device_type = "cpu";
62 			compatible = "arm,cortex-a9";
63 			reg = <0>;
64 		};
65 	};
66 
67 	soc {
68 		internal-regs {
69 			pinctrl@18000 {
70 				compatible = "marvell,mv88f6810-pinctrl";
71 			};
72 		};
73 
74 		pcie-controller {
75 			compatible = "marvell,armada-370-pcie";
76 			status = "disabled";
77 			device_type = "pci";
78 
79 			#address-cells = <3>;
80 			#size-cells = <2>;
81 
82 			msi-parent = <&mpic>;
83 			bus-range = <0x00 0xff>;
84 
85 			ranges =
86 			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
87 				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
88 				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
89 				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
90 				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
91 				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
92 				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
93 				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
94 				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
95 				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */>;
96 
97 			/* x1 port */
98 			pcie@1,0 {
99 				device_type = "pci";
100 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
101 				reg = <0x0800 0 0 0 0>;
102 				#address-cells = <3>;
103 				#size-cells = <2>;
104 				#interrupt-cells = <1>;
105 				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
106 					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
107 				interrupt-map-mask = <0 0 0 0>;
108 				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
109 				marvell,pcie-port = <0>;
110 				marvell,pcie-lane = <0>;
111 				clocks = <&gateclk 8>;
112 				status = "disabled";
113 			};
114 
115 			/* x1 port */
116 			pcie@2,0 {
117 				device_type = "pci";
118 				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
119 				reg = <0x1000 0 0 0 0>;
120 				#address-cells = <3>;
121 				#size-cells = <2>;
122 				#interrupt-cells = <1>;
123 				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
124 					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
125 				interrupt-map-mask = <0 0 0 0>;
126 				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
127 				marvell,pcie-port = <1>;
128 				marvell,pcie-lane = <0>;
129 				clocks = <&gateclk 5>;
130 				status = "disabled";
131 			};
132 
133 			/* x1 port */
134 			pcie@3,0 {
135 				device_type = "pci";
136 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
137 				reg = <0x1800 0 0 0 0>;
138 				#address-cells = <3>;
139 				#size-cells = <2>;
140 				#interrupt-cells = <1>;
141 				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
142 					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
143 				interrupt-map-mask = <0 0 0 0>;
144 				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
145 				marvell,pcie-port = <2>;
146 				marvell,pcie-lane = <0>;
147 				clocks = <&gateclk 6>;
148 				status = "disabled";
149 			};
150 		};
151 	};
152 };
153