xref: /openbmc/u-boot/arch/arm/dts/armada-37xx.dtsi (revision ec90ac73)
1/*
2 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
3 *
4 * Copyright (C) 2016 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPL or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 *  a) This file is free software; you can redistribute it and/or
14 *     modify it under the terms of the GNU General Public License as
15 *     published by the Free Software Foundation; either version 2 of the
16 *     License, or (at your option) any later version.
17 *
18 *     This file is distributed in the hope that it will be useful
19 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
20 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21 *     GNU General Public License for more details.
22 *
23 * Or, alternatively
24 *
25 *  b) Permission is hereby granted, free of charge, to any person
26 *     obtaining a copy of this software and associated documentation
27 *     files (the "Software"), to deal in the Software without
28 *     restriction, including without limitation the rights to use
29 *     copy, modify, merge, publish, distribute, sublicense, and/or
30 *     sell copies of the Software, and to permit persons to whom the
31 *     Software is furnished to do so, subject to the following
32 *     conditions:
33 *
34 *     The above copyright notice and this permission notice shall be
35 *     included in all copies or substantial portions of the Software.
36 *
37 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
38 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
42 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 *     OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/comphy/comphy_data.h>
49
50/ {
51	model = "Marvell Armada 37xx SoC";
52	compatible = "marvell,armada3700";
53	interrupt-parent = <&gic>;
54	#address-cells = <2>;
55	#size-cells = <2>;
56
57	aliases {
58		serial0 = &uart0;
59	};
60
61	cpus {
62		#address-cells = <1>;
63		#size-cells = <0>;
64		cpu@0 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53", "arm,armv8";
67			reg = <0>;
68			enable-method = "psci";
69		};
70	};
71
72	psci {
73		compatible = "arm,psci-0.2";
74		method = "smc";
75	};
76
77	timer {
78		compatible = "arm,armv8-timer";
79		interrupts = <GIC_PPI 13
80			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
81			     <GIC_PPI 14
82			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
83			     <GIC_PPI 11
84			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
85			     <GIC_PPI 10
86			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
87	};
88
89	soc {
90		compatible = "simple-bus";
91		#address-cells = <2>;
92		#size-cells = <2>;
93		ranges;
94
95		internal-regs {
96			#address-cells = <1>;
97			#size-cells = <1>;
98			compatible = "simple-bus";
99			/* 32M internal register @ 0xd000_0000 */
100			ranges = <0x0 0x0 0xd0000000 0x2000000>;
101
102			uart0: serial@12000 {
103				compatible = "marvell,armada-3700-uart";
104				reg = <0x12000 0x400>;
105				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
106				status = "disabled";
107			};
108
109			usb3: usb@58000 {
110				compatible = "marvell,armada3700-xhci",
111				"generic-xhci";
112				reg = <0x58000 0x4000>;
113				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
114				status = "disabled";
115			};
116
117			usb2: usb@5e000 {
118				compatible = "marvell,armada3700-ehci";
119				reg = <0x5e000 0x450>;
120				status = "disabled";
121			};
122
123			xor@60900 {
124				compatible = "marvell,armada-3700-xor";
125				reg = <0x60900 0x100
126				       0x60b00 0x100>;
127
128				xor10 {
129					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
130				};
131				xor11 {
132					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
133				};
134			};
135
136			sata: sata@e0000 {
137				compatible = "marvell,armada-3700-ahci";
138				reg = <0xe0000 0x2000>;
139				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
140				status = "disabled";
141			};
142
143			gic: interrupt-controller@1d00000 {
144				compatible = "arm,gic-v3";
145				#interrupt-cells = <3>;
146				interrupt-controller;
147				reg = <0x1d00000 0x10000>, /* GICD */
148				      <0x1d40000 0x40000>; /* GICR */
149			};
150
151			eth0: neta@30000 {
152				compatible = "marvell,armada-3700-neta";
153				reg = <0x30000 0x20>;
154				status = "disabled";
155			};
156
157			eth1: neta@40000 {
158				compatible = "marvell,armada-3700-neta";
159				reg = <0x40000 0x20>;
160				status = "disabled";
161			};
162
163			i2c0: i2c@11000 {
164				compatible = "marvell,armada-3700-i2c";
165				reg = <0x11000 0x100>;
166				status = "disabled";
167			};
168
169			spi0: spi@10600 {
170				compatible = "marvell,armada-3700-spi";
171				reg = <0x10600 0x50>;
172				#address-cells = <1>;
173				#size-cells = <0>;
174				#clock-cells = <0>;
175				clock-frequency = <160000>;
176				spi-max-frequency = <40000>;
177				status = "disabled";
178			};
179
180			comphy: comphy@18300 {
181				compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
182				reg = <0x18300 0x28>,
183				      <0x1f300 0x3d000>;
184				mux-bitcount = <1>;
185				max-lanes = <2>;
186			};
187		};
188	};
189};
190