1/* 2 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/comphy/comphy_data.h> 49 50/ { 51 model = "Marvell Armada 37xx SoC"; 52 compatible = "marvell,armada3700"; 53 interrupt-parent = <&gic>; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 57 aliases { 58 serial0 = &uart0; 59 }; 60 61 cpus { 62 #address-cells = <1>; 63 #size-cells = <0>; 64 cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 reg = <0>; 68 enable-method = "psci"; 69 }; 70 }; 71 72 psci { 73 compatible = "arm,psci-0.2"; 74 method = "smc"; 75 }; 76 77 timer { 78 compatible = "arm,armv8-timer"; 79 interrupts = <GIC_PPI 13 80 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 81 <GIC_PPI 14 82 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 83 <GIC_PPI 11 84 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 85 <GIC_PPI 10 86 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 87 }; 88 89 soc { 90 compatible = "simple-bus"; 91 #address-cells = <2>; 92 #size-cells = <2>; 93 ranges; 94 95 internal-regs { 96 #address-cells = <1>; 97 #size-cells = <1>; 98 compatible = "simple-bus"; 99 /* 32M internal register @ 0xd000_0000 */ 100 ranges = <0x0 0x0 0xd0000000 0x2000000>; 101 102 uart0: serial@12000 { 103 compatible = "marvell,armada-3700-uart"; 104 reg = <0x12000 0x400>; 105 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 106 status = "disabled"; 107 }; 108 109 pinctrl_nb: pinctrl-nb@13800 { 110 compatible = "marvell,armada3710-nb-pinctrl", 111 "syscon", "simple-mfd"; 112 reg = <0x13800 0x100>, <0x13C00 0x20>; 113 gpionb: gpionb { 114 #gpio-cells = <2>; 115 gpio-ranges = <&pinctrl_nb 0 0 36>; 116 gpio-controller; 117 interrupts = 118 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 130 131 }; 132 133 spi_quad_pins: spi-quad-pins { 134 groups = "spi_quad"; 135 function = "spi"; 136 }; 137 138 i2c1_pins: i2c1-pins { 139 groups = "i2c1"; 140 function = "i2c"; 141 }; 142 143 i2c2_pins: i2c2-pins { 144 groups = "i2c2"; 145 function = "i2c"; 146 }; 147 148 uart1_pins: uart1-pins { 149 groups = "uart1"; 150 function = "uart"; 151 }; 152 153 uart2_pins: uart2-pins { 154 groups = "uart2"; 155 function = "uart"; 156 }; 157 }; 158 159 pinctrl_sb: pinctrl-sb@18800 { 160 compatible = "marvell,armada3710-sb-pinctrl", 161 "syscon", "simple-mfd"; 162 reg = <0x18800 0x100>, <0x18C00 0x20>; 163 gpiosb: gpiosb { 164 #gpio-cells = <2>; 165 gpio-ranges = <&pinctrl_sb 0 0 29>; 166 gpio-controller; 167 interrupts = 168 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 173 }; 174 175 rgmii_pins: mii-pins { 176 groups = "rgmii"; 177 function = "mii"; 178 }; 179 180 }; 181 182 usb3: usb@58000 { 183 compatible = "marvell,armada3700-xhci", 184 "generic-xhci"; 185 reg = <0x58000 0x4000>; 186 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 187 status = "disabled"; 188 }; 189 190 usb2: usb@5e000 { 191 compatible = "marvell,armada3700-ehci"; 192 reg = <0x5e000 0x450>; 193 status = "disabled"; 194 }; 195 196 xor@60900 { 197 compatible = "marvell,armada-3700-xor"; 198 reg = <0x60900 0x100 199 0x60b00 0x100>; 200 201 xor10 { 202 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 203 }; 204 xor11 { 205 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 206 }; 207 }; 208 209 sdhci0: sdhci@d0000 { 210 compatible = "marvell,armada-3700-sdhci", 211 "marvell,sdhci-xenon"; 212 reg = <0xd0000 0x300 213 0x1e808 0x4>; 214 status = "disabled"; 215 }; 216 217 sdhci1: sdhci@d8000 { 218 compatible = "marvell,armada-3700-sdhci", 219 "marvell,sdhci-xenon"; 220 reg = <0xd8000 0x300 221 0x17808 0x4>; 222 status = "disabled"; 223 }; 224 225 sata: sata@e0000 { 226 compatible = "marvell,armada-3700-ahci"; 227 reg = <0xe0000 0x2000>; 228 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 229 status = "disabled"; 230 }; 231 232 gic: interrupt-controller@1d00000 { 233 compatible = "arm,gic-v3"; 234 #interrupt-cells = <3>; 235 interrupt-controller; 236 reg = <0x1d00000 0x10000>, /* GICD */ 237 <0x1d40000 0x40000>; /* GICR */ 238 }; 239 240 eth0: neta@30000 { 241 compatible = "marvell,armada-3700-neta"; 242 reg = <0x30000 0x20>; 243 status = "disabled"; 244 }; 245 246 eth1: neta@40000 { 247 compatible = "marvell,armada-3700-neta"; 248 reg = <0x40000 0x20>; 249 status = "disabled"; 250 }; 251 252 i2c0: i2c@11000 { 253 compatible = "marvell,armada-3700-i2c"; 254 reg = <0x11000 0x100>; 255 status = "disabled"; 256 }; 257 258 spi0: spi@10600 { 259 compatible = "marvell,armada-3700-spi"; 260 reg = <0x10600 0x50>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 #clock-cells = <0>; 264 clock-frequency = <160000>; 265 spi-max-frequency = <40000>; 266 status = "disabled"; 267 }; 268 269 pinctl0: pinctl@13830 { /* north bridge */ 270 compatible = "marvell,armada-3700-pinctl"; 271 bank-name = "armada-3700-nb"; 272 reg = <0x13830 0x4>; 273 pin-count = <36>; 274 }; 275 276 pinctl1: pinctl@18830 { /* south bridge */ 277 compatible = "marvell,armada-3700-pinctl"; 278 bank-name = "armada-3700-sb"; 279 reg = <0x18830 0x4>; 280 pin-count = <30>; 281 }; 282 283 comphy: comphy@18300 { 284 compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 285 reg = <0x18300 0x28>, 286 <0x1f300 0x3d000>; 287 mux-bitcount = <1>; 288 max-lanes = <2>; 289 }; 290 }; 291 }; 292}; 293