1/* 2 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/comphy/comphy_data.h> 49#include <dt-bindings/gpio/gpio.h> 50 51/ { 52 model = "Marvell Armada 37xx SoC"; 53 compatible = "marvell,armada3700"; 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 serial0 = &uart0; 60 }; 61 62 cpus { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 reg = <0>; 69 enable-method = "psci"; 70 }; 71 }; 72 73 psci { 74 compatible = "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 timer { 79 compatible = "arm,armv8-timer"; 80 interrupts = <GIC_PPI 13 81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 14 83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 11 85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 86 <GIC_PPI 10 87 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 88 }; 89 90 soc { 91 compatible = "simple-bus"; 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 96 internal-regs { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 compatible = "simple-bus"; 100 /* 32M internal register @ 0xd000_0000 */ 101 ranges = <0x0 0x0 0xd0000000 0x2000000>; 102 103 uart0: serial@12000 { 104 compatible = "marvell,armada-3700-uart"; 105 reg = <0x12000 0x400>; 106 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 107 status = "disabled"; 108 }; 109 110 pinctrl_nb: pinctrl-nb@13800 { 111 compatible = "marvell,armada3710-nb-pinctrl", 112 "syscon", "simple-mfd"; 113 reg = <0x13800 0x100>, <0x13C00 0x20>; 114 gpionb: gpionb { 115 #gpio-cells = <2>; 116 gpio-ranges = <&pinctrl_nb 0 0 36>; 117 gpio-controller; 118 interrupts = 119 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 131 132 }; 133 134 spi_quad_pins: spi-quad-pins { 135 groups = "spi_quad"; 136 function = "spi"; 137 }; 138 139 i2c1_pins: i2c1-pins { 140 groups = "i2c1"; 141 function = "i2c"; 142 }; 143 144 i2c2_pins: i2c2-pins { 145 groups = "i2c2"; 146 function = "i2c"; 147 }; 148 149 uart1_pins: uart1-pins { 150 groups = "uart1"; 151 function = "uart"; 152 }; 153 154 uart2_pins: uart2-pins { 155 groups = "uart2"; 156 function = "uart"; 157 }; 158 159 mmc_pins: mmc-pins { 160 groups = "emmc_nb"; 161 function = "emmc"; 162 }; 163 }; 164 165 pinctrl_sb: pinctrl-sb@18800 { 166 compatible = "marvell,armada3710-sb-pinctrl", 167 "syscon", "simple-mfd"; 168 reg = <0x18800 0x100>, <0x18C00 0x20>; 169 gpiosb: gpiosb { 170 #gpio-cells = <2>; 171 gpio-ranges = <&pinctrl_sb 0 0 30>; 172 gpio-controller; 173 interrupts = 174 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 179 }; 180 181 rgmii_pins: mii-pins { 182 groups = "rgmii"; 183 function = "mii"; 184 }; 185 186 smi_pins: smi-pins { 187 groups = "smi"; 188 function = "smi"; 189 }; 190 191 sdio_pins: sdio-pins { 192 groups = "sdio_sb"; 193 function = "sdio"; 194 }; 195 196 pcie_pins: pcie-pins { 197 groups = "pcie1"; 198 function = "gpio"; 199 }; 200 }; 201 202 usb3: usb@58000 { 203 compatible = "marvell,armada3700-xhci", 204 "generic-xhci"; 205 reg = <0x58000 0x4000>; 206 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 207 status = "disabled"; 208 }; 209 210 usb2: usb@5e000 { 211 compatible = "marvell,armada3700-ehci"; 212 reg = <0x5e000 0x450>; 213 status = "disabled"; 214 }; 215 216 xor@60900 { 217 compatible = "marvell,armada-3700-xor"; 218 reg = <0x60900 0x100 219 0x60b00 0x100>; 220 221 xor10 { 222 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 223 }; 224 xor11 { 225 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 226 }; 227 }; 228 229 sdhci0: sdhci@d0000 { 230 compatible = "marvell,armada-3700-sdhci", 231 "marvell,sdhci-xenon"; 232 reg = <0xd0000 0x300 233 0x1e808 0x4>; 234 status = "disabled"; 235 }; 236 237 sdhci1: sdhci@d8000 { 238 compatible = "marvell,armada-3700-sdhci", 239 "marvell,sdhci-xenon"; 240 reg = <0xd8000 0x300 241 0x17808 0x4>; 242 status = "disabled"; 243 }; 244 245 sata: sata@e0000 { 246 compatible = "marvell,armada-3700-ahci"; 247 reg = <0xe0000 0x2000>; 248 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 249 status = "disabled"; 250 }; 251 252 gic: interrupt-controller@1d00000 { 253 compatible = "arm,gic-v3"; 254 #interrupt-cells = <3>; 255 interrupt-controller; 256 reg = <0x1d00000 0x10000>, /* GICD */ 257 <0x1d40000 0x40000>; /* GICR */ 258 }; 259 260 eth0: neta@30000 { 261 compatible = "marvell,armada-3700-neta"; 262 reg = <0x30000 0x20>; 263 status = "disabled"; 264 }; 265 266 eth1: neta@40000 { 267 compatible = "marvell,armada-3700-neta"; 268 reg = <0x40000 0x20>; 269 status = "disabled"; 270 }; 271 272 i2c0: i2c@11000 { 273 compatible = "marvell,armada-3700-i2c"; 274 reg = <0x11000 0x100>; 275 status = "disabled"; 276 }; 277 278 spi0: spi@10600 { 279 compatible = "marvell,armada-3700-spi"; 280 reg = <0x10600 0x50>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 #clock-cells = <0>; 284 clock-frequency = <160000>; 285 spi-max-frequency = <40000>; 286 status = "disabled"; 287 }; 288 289 comphy: comphy@18300 { 290 compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 291 reg = <0x18300 0x28>, 292 <0x1f300 0x3d000>; 293 mux-bitcount = <1>; 294 max-lanes = <2>; 295 }; 296 }; 297 298 pcie0: pcie@d0070000 { 299 compatible = "marvell,armada-37xx-pcie"; 300 reg = <0 0xd0070000 0 0x20000>; 301 #address-cells = <3>; 302 #size-cells = <2>; 303 device_type = "pci"; 304 num-lanes = <1>; 305 status = "disabled"; 306 307 bus-range = <0 0xff>; 308 ranges = <0x82000000 0 0xe8000000 309 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 310 0x81000000 0 0xe9000000 311 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 312 }; 313 }; 314}; 315