1/* 2 * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3 * 4 * Copyright (C) 2016 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is dual-licensed: you can use it either under the terms 9 * of the GPL or the X11 license, at your option. Note that this dual 10 * licensing only applies to this file, and not this project as a 11 * whole. 12 * 13 * a) This file is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of the 16 * License, or (at your option) any later version. 17 * 18 * This file is distributed in the hope that it will be useful 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * Or, alternatively 24 * 25 * b) Permission is hereby granted, free of charge, to any person 26 * obtaining a copy of this software and associated documentation 27 * files (the "Software"), to deal in the Software without 28 * restriction, including without limitation the rights to use 29 * copy, modify, merge, publish, distribute, sublicense, and/or 30 * sell copies of the Software, and to permit persons to whom the 31 * Software is furnished to do so, subject to the following 32 * conditions: 33 * 34 * The above copyright notice and this permission notice shall be 35 * included in all copies or substantial portions of the Software. 36 * 37 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44 * OTHER DEALINGS IN THE SOFTWARE. 45 */ 46 47#include <dt-bindings/interrupt-controller/arm-gic.h> 48#include <dt-bindings/comphy/comphy_data.h> 49#include <dt-bindings/gpio/gpio.h> 50 51/ { 52 model = "Marvell Armada 37xx SoC"; 53 compatible = "marvell,armada3700"; 54 interrupt-parent = <&gic>; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 58 aliases { 59 serial0 = &uart0; 60 }; 61 62 cpus { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 cpu@0 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 reg = <0>; 69 enable-method = "psci"; 70 }; 71 }; 72 73 psci { 74 compatible = "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 timer { 79 compatible = "arm,armv8-timer"; 80 interrupts = <GIC_PPI 13 81 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 14 83 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 11 85 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 86 <GIC_PPI 10 87 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 88 }; 89 90 soc { 91 compatible = "simple-bus"; 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 96 internal-regs { 97 #address-cells = <1>; 98 #size-cells = <1>; 99 compatible = "simple-bus"; 100 /* 32M internal register @ 0xd000_0000 */ 101 ranges = <0x0 0x0 0xd0000000 0x2000000>; 102 103 uart0: serial@12000 { 104 compatible = "marvell,armada-3700-uart"; 105 reg = <0x12000 0x400>; 106 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 107 status = "disabled"; 108 }; 109 110 wdt: watchdog-timer@8300 { 111 compatible = "marvell,armada-3700-wdt"; 112 reg = <0xd064 0x4>, 113 <0x8300 0x40>; 114 }; 115 116 nb_periph_clk: nb-periph-clk@13000 { 117 compatible = "marvell,armada-3700-periph-clock-nb"; 118 reg = <0x13000 0x100>; 119 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>; 120 #clock-cells = <1>; 121 }; 122 123 sb_periph_clk: sb-periph-clk@18000 { 124 compatible = "marvell,armada-3700-periph-clock-sb"; 125 reg = <0x18000 0x100>; 126 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>; 127 #clock-cells = <1>; 128 }; 129 130 tbg: tbg@13200 { 131 compatible = "marvell,armada-3700-tbg-clock"; 132 reg = <0x13200 0x100>; 133 #clock-cells = <1>; 134 }; 135 136 pinctrl_nb: pinctrl-nb@13800 { 137 compatible = "marvell,armada3710-nb-pinctrl", 138 "syscon", "simple-mfd"; 139 reg = <0x13800 0x100>, <0x13C00 0x20>; 140 gpionb: gpionb { 141 #gpio-cells = <2>; 142 gpio-ranges = <&pinctrl_nb 0 0 36>; 143 gpio-controller; 144 interrupts = 145 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 157 158 }; 159 160 spi_quad_pins: spi-quad-pins { 161 groups = "spi_quad"; 162 function = "spi"; 163 }; 164 165 i2c1_pins: i2c1-pins { 166 groups = "i2c1"; 167 function = "i2c"; 168 }; 169 170 i2c2_pins: i2c2-pins { 171 groups = "i2c2"; 172 function = "i2c"; 173 }; 174 175 uart1_pins: uart1-pins { 176 groups = "uart1"; 177 function = "uart"; 178 }; 179 180 uart2_pins: uart2-pins { 181 groups = "uart2"; 182 function = "uart"; 183 }; 184 185 mmc_pins: mmc-pins { 186 groups = "emmc_nb"; 187 function = "emmc"; 188 }; 189 }; 190 191 pinctrl_sb: pinctrl-sb@18800 { 192 compatible = "marvell,armada3710-sb-pinctrl", 193 "syscon", "simple-mfd"; 194 reg = <0x18800 0x100>, <0x18C00 0x20>; 195 gpiosb: gpiosb { 196 #gpio-cells = <2>; 197 gpio-ranges = <&pinctrl_sb 0 0 30>; 198 gpio-controller; 199 interrupts = 200 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 205 }; 206 207 rgmii_pins: mii-pins { 208 groups = "rgmii"; 209 function = "mii"; 210 }; 211 212 smi_pins: smi-pins { 213 groups = "smi"; 214 function = "smi"; 215 }; 216 217 sdio_pins: sdio-pins { 218 groups = "sdio_sb"; 219 function = "sdio"; 220 }; 221 222 pcie_pins: pcie-pins { 223 groups = "pcie1"; 224 function = "gpio"; 225 }; 226 }; 227 228 usb3: usb@58000 { 229 compatible = "marvell,armada3700-xhci", 230 "generic-xhci"; 231 reg = <0x58000 0x4000>; 232 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 233 status = "disabled"; 234 }; 235 236 usb2: usb@5e000 { 237 compatible = "marvell,armada3700-ehci"; 238 reg = <0x5e000 0x450>; 239 status = "disabled"; 240 }; 241 242 xor@60900 { 243 compatible = "marvell,armada-3700-xor"; 244 reg = <0x60900 0x100 245 0x60b00 0x100>; 246 247 xor10 { 248 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 249 }; 250 xor11 { 251 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 252 }; 253 }; 254 255 sdhci0: sdhci@d0000 { 256 compatible = "marvell,armada-3700-sdhci", 257 "marvell,sdhci-xenon"; 258 reg = <0xd0000 0x300 259 0x1e808 0x4>; 260 status = "disabled"; 261 }; 262 263 sdhci1: sdhci@d8000 { 264 compatible = "marvell,armada-3700-sdhci", 265 "marvell,sdhci-xenon"; 266 reg = <0xd8000 0x300 267 0x17808 0x4>; 268 status = "disabled"; 269 }; 270 271 sata: sata@e0000 { 272 compatible = "marvell,armada-3700-ahci"; 273 reg = <0xe0000 0x2000>; 274 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 275 status = "disabled"; 276 }; 277 278 gic: interrupt-controller@1d00000 { 279 compatible = "arm,gic-v3"; 280 #interrupt-cells = <3>; 281 interrupt-controller; 282 reg = <0x1d00000 0x10000>, /* GICD */ 283 <0x1d40000 0x40000>; /* GICR */ 284 }; 285 286 eth0: neta@30000 { 287 compatible = "marvell,armada-3700-neta"; 288 reg = <0x30000 0x20>; 289 status = "disabled"; 290 }; 291 292 eth1: neta@40000 { 293 compatible = "marvell,armada-3700-neta"; 294 reg = <0x40000 0x20>; 295 status = "disabled"; 296 }; 297 298 i2c0: i2c@11000 { 299 compatible = "marvell,armada-3700-i2c"; 300 reg = <0x11000 0x100>; 301 status = "disabled"; 302 }; 303 304 spi0: spi@10600 { 305 compatible = "marvell,armada-3700-spi"; 306 reg = <0x10600 0x50>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 #clock-cells = <0>; 310 spi-max-frequency = <50000000>; 311 clocks = <&nb_periph_clk 7>; 312 status = "disabled"; 313 }; 314 315 comphy: comphy@18300 { 316 compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 317 reg = <0x18300 0x28>, 318 <0x1f300 0x3d000>; 319 mux-bitcount = <4>; 320 mux-lane-order = <1 0 2>; 321 max-lanes = <3>; 322 }; 323 }; 324 325 pcie0: pcie@d0070000 { 326 compatible = "marvell,armada-37xx-pcie"; 327 reg = <0 0xd0070000 0 0x20000>; 328 #address-cells = <3>; 329 #size-cells = <2>; 330 device_type = "pci"; 331 num-lanes = <1>; 332 status = "disabled"; 333 334 bus-range = <0 0xff>; 335 ranges = <0x82000000 0 0xe8000000 336 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 337 0x81000000 0 0xe9000000 338 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 339 }; 340 }; 341}; 342