1850db82fSStefan Roese/* 2850db82fSStefan Roese * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3850db82fSStefan Roese * 4850db82fSStefan Roese * Copyright (C) 2016 Marvell 5850db82fSStefan Roese * 6850db82fSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 7850db82fSStefan Roese * 8850db82fSStefan Roese * This file is dual-licensed: you can use it either under the terms 9850db82fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 10850db82fSStefan Roese * licensing only applies to this file, and not this project as a 11850db82fSStefan Roese * whole. 12850db82fSStefan Roese * 13850db82fSStefan Roese * a) This file is free software; you can redistribute it and/or 14850db82fSStefan Roese * modify it under the terms of the GNU General Public License as 15850db82fSStefan Roese * published by the Free Software Foundation; either version 2 of the 16850db82fSStefan Roese * License, or (at your option) any later version. 17850db82fSStefan Roese * 18850db82fSStefan Roese * This file is distributed in the hope that it will be useful 19850db82fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 20850db82fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21850db82fSStefan Roese * GNU General Public License for more details. 22850db82fSStefan Roese * 23850db82fSStefan Roese * Or, alternatively 24850db82fSStefan Roese * 25850db82fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 26850db82fSStefan Roese * obtaining a copy of this software and associated documentation 27850db82fSStefan Roese * files (the "Software"), to deal in the Software without 28850db82fSStefan Roese * restriction, including without limitation the rights to use 29850db82fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 30850db82fSStefan Roese * sell copies of the Software, and to permit persons to whom the 31850db82fSStefan Roese * Software is furnished to do so, subject to the following 32850db82fSStefan Roese * conditions: 33850db82fSStefan Roese * 34850db82fSStefan Roese * The above copyright notice and this permission notice shall be 35850db82fSStefan Roese * included in all copies or substantial portions of the Software. 36850db82fSStefan Roese * 37850db82fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38850db82fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39850db82fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40850db82fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41850db82fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42850db82fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43850db82fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44850db82fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 45850db82fSStefan Roese */ 46850db82fSStefan Roese 47850db82fSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 4856d53956SStefan Roese#include <dt-bindings/comphy/comphy_data.h> 49850db82fSStefan Roese 50850db82fSStefan Roese/ { 51850db82fSStefan Roese model = "Marvell Armada 37xx SoC"; 52850db82fSStefan Roese compatible = "marvell,armada3700"; 53850db82fSStefan Roese interrupt-parent = <&gic>; 54850db82fSStefan Roese #address-cells = <2>; 55850db82fSStefan Roese #size-cells = <2>; 56850db82fSStefan Roese 57850db82fSStefan Roese aliases { 58850db82fSStefan Roese serial0 = &uart0; 59850db82fSStefan Roese }; 60850db82fSStefan Roese 61850db82fSStefan Roese cpus { 62850db82fSStefan Roese #address-cells = <1>; 63850db82fSStefan Roese #size-cells = <0>; 64850db82fSStefan Roese cpu@0 { 65850db82fSStefan Roese device_type = "cpu"; 66850db82fSStefan Roese compatible = "arm,cortex-a53", "arm,armv8"; 67850db82fSStefan Roese reg = <0>; 68850db82fSStefan Roese enable-method = "psci"; 69850db82fSStefan Roese }; 70850db82fSStefan Roese }; 71850db82fSStefan Roese 72850db82fSStefan Roese psci { 73850db82fSStefan Roese compatible = "arm,psci-0.2"; 74850db82fSStefan Roese method = "smc"; 75850db82fSStefan Roese }; 76850db82fSStefan Roese 77850db82fSStefan Roese timer { 78850db82fSStefan Roese compatible = "arm,armv8-timer"; 79850db82fSStefan Roese interrupts = <GIC_PPI 13 80850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 81850db82fSStefan Roese <GIC_PPI 14 82850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 83850db82fSStefan Roese <GIC_PPI 11 84850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 85850db82fSStefan Roese <GIC_PPI 10 86850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 87850db82fSStefan Roese }; 88850db82fSStefan Roese 89850db82fSStefan Roese soc { 90850db82fSStefan Roese compatible = "simple-bus"; 91850db82fSStefan Roese #address-cells = <2>; 92850db82fSStefan Roese #size-cells = <2>; 93850db82fSStefan Roese ranges; 94850db82fSStefan Roese 95850db82fSStefan Roese internal-regs { 96850db82fSStefan Roese #address-cells = <1>; 97850db82fSStefan Roese #size-cells = <1>; 98850db82fSStefan Roese compatible = "simple-bus"; 99850db82fSStefan Roese /* 32M internal register @ 0xd000_0000 */ 100850db82fSStefan Roese ranges = <0x0 0x0 0xd0000000 0x2000000>; 101850db82fSStefan Roese 102850db82fSStefan Roese uart0: serial@12000 { 103850db82fSStefan Roese compatible = "marvell,armada-3700-uart"; 104850db82fSStefan Roese reg = <0x12000 0x400>; 105850db82fSStefan Roese interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 106850db82fSStefan Roese status = "disabled"; 107850db82fSStefan Roese }; 108850db82fSStefan Roese 109850db82fSStefan Roese usb3: usb@58000 { 110850db82fSStefan Roese compatible = "marvell,armada3700-xhci", 111850db82fSStefan Roese "generic-xhci"; 112850db82fSStefan Roese reg = <0x58000 0x4000>; 113850db82fSStefan Roese interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 114850db82fSStefan Roese status = "disabled"; 115850db82fSStefan Roese }; 116850db82fSStefan Roese 117f733228aSStefan Roese usb2: usb@5e000 { 118f733228aSStefan Roese compatible = "marvell,armada3700-ehci"; 119f733228aSStefan Roese reg = <0x5e000 0x450>; 120f733228aSStefan Roese status = "disabled"; 121f733228aSStefan Roese }; 122f733228aSStefan Roese 123850db82fSStefan Roese xor@60900 { 124850db82fSStefan Roese compatible = "marvell,armada-3700-xor"; 125850db82fSStefan Roese reg = <0x60900 0x100 126850db82fSStefan Roese 0x60b00 0x100>; 127850db82fSStefan Roese 128850db82fSStefan Roese xor10 { 129850db82fSStefan Roese interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 130850db82fSStefan Roese }; 131850db82fSStefan Roese xor11 { 132850db82fSStefan Roese interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 133850db82fSStefan Roese }; 134850db82fSStefan Roese }; 135850db82fSStefan Roese 136*cbe0ece8SStefan Roese sdhci0: sdhci@d0000 { 137*cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 138*cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 139*cbe0ece8SStefan Roese reg = <0xd0000 0x300 140*cbe0ece8SStefan Roese 0x1e808 0x4>; 141*cbe0ece8SStefan Roese status = "disabled"; 142*cbe0ece8SStefan Roese }; 143*cbe0ece8SStefan Roese 144*cbe0ece8SStefan Roese sdhci1: sdhci@d8000 { 145*cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 146*cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 147*cbe0ece8SStefan Roese reg = <0xd8000 0x300 148*cbe0ece8SStefan Roese 0x17808 0x4>; 149*cbe0ece8SStefan Roese status = "disabled"; 150*cbe0ece8SStefan Roese }; 151*cbe0ece8SStefan Roese 152850db82fSStefan Roese sata: sata@e0000 { 153850db82fSStefan Roese compatible = "marvell,armada-3700-ahci"; 154850db82fSStefan Roese reg = <0xe0000 0x2000>; 155850db82fSStefan Roese interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 156850db82fSStefan Roese status = "disabled"; 157850db82fSStefan Roese }; 158850db82fSStefan Roese 159850db82fSStefan Roese gic: interrupt-controller@1d00000 { 160850db82fSStefan Roese compatible = "arm,gic-v3"; 161850db82fSStefan Roese #interrupt-cells = <3>; 162850db82fSStefan Roese interrupt-controller; 163850db82fSStefan Roese reg = <0x1d00000 0x10000>, /* GICD */ 164850db82fSStefan Roese <0x1d40000 0x40000>; /* GICR */ 165850db82fSStefan Roese }; 166cdccf9c1SStefan Roese 1673f84e2e8SStefan Roese eth0: neta@30000 { 1683f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 1693f84e2e8SStefan Roese reg = <0x30000 0x20>; 1703f84e2e8SStefan Roese status = "disabled"; 1713f84e2e8SStefan Roese }; 1723f84e2e8SStefan Roese 1733f84e2e8SStefan Roese eth1: neta@40000 { 1743f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 1753f84e2e8SStefan Roese reg = <0x40000 0x20>; 1763f84e2e8SStefan Roese status = "disabled"; 1773f84e2e8SStefan Roese }; 1783f84e2e8SStefan Roese 1799e9e63c0SStefan Roese i2c0: i2c@11000 { 1809e9e63c0SStefan Roese compatible = "marvell,armada-3700-i2c"; 1819e9e63c0SStefan Roese reg = <0x11000 0x100>; 1829e9e63c0SStefan Roese status = "disabled"; 1839e9e63c0SStefan Roese }; 1849e9e63c0SStefan Roese 185cdccf9c1SStefan Roese spi0: spi@10600 { 186cdccf9c1SStefan Roese compatible = "marvell,armada-3700-spi"; 187cdccf9c1SStefan Roese reg = <0x10600 0x50>; 188cdccf9c1SStefan Roese #address-cells = <1>; 189cdccf9c1SStefan Roese #size-cells = <0>; 190cdccf9c1SStefan Roese #clock-cells = <0>; 191cdccf9c1SStefan Roese clock-frequency = <160000>; 192cdccf9c1SStefan Roese spi-max-frequency = <40000>; 193cdccf9c1SStefan Roese status = "disabled"; 194cdccf9c1SStefan Roese }; 19556d53956SStefan Roese 19656d53956SStefan Roese comphy: comphy@18300 { 19756d53956SStefan Roese compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 19856d53956SStefan Roese reg = <0x18300 0x28>, 19956d53956SStefan Roese <0x1f300 0x3d000>; 20056d53956SStefan Roese mux-bitcount = <1>; 20156d53956SStefan Roese max-lanes = <2>; 20256d53956SStefan Roese }; 203850db82fSStefan Roese }; 204850db82fSStefan Roese }; 205850db82fSStefan Roese}; 206