1*850db82fSStefan Roese/* 2*850db82fSStefan Roese * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3*850db82fSStefan Roese * 4*850db82fSStefan Roese * Copyright (C) 2016 Marvell 5*850db82fSStefan Roese * 6*850db82fSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 7*850db82fSStefan Roese * 8*850db82fSStefan Roese * This file is dual-licensed: you can use it either under the terms 9*850db82fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 10*850db82fSStefan Roese * licensing only applies to this file, and not this project as a 11*850db82fSStefan Roese * whole. 12*850db82fSStefan Roese * 13*850db82fSStefan Roese * a) This file is free software; you can redistribute it and/or 14*850db82fSStefan Roese * modify it under the terms of the GNU General Public License as 15*850db82fSStefan Roese * published by the Free Software Foundation; either version 2 of the 16*850db82fSStefan Roese * License, or (at your option) any later version. 17*850db82fSStefan Roese * 18*850db82fSStefan Roese * This file is distributed in the hope that it will be useful 19*850db82fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 20*850db82fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21*850db82fSStefan Roese * GNU General Public License for more details. 22*850db82fSStefan Roese * 23*850db82fSStefan Roese * Or, alternatively 24*850db82fSStefan Roese * 25*850db82fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 26*850db82fSStefan Roese * obtaining a copy of this software and associated documentation 27*850db82fSStefan Roese * files (the "Software"), to deal in the Software without 28*850db82fSStefan Roese * restriction, including without limitation the rights to use 29*850db82fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 30*850db82fSStefan Roese * sell copies of the Software, and to permit persons to whom the 31*850db82fSStefan Roese * Software is furnished to do so, subject to the following 32*850db82fSStefan Roese * conditions: 33*850db82fSStefan Roese * 34*850db82fSStefan Roese * The above copyright notice and this permission notice shall be 35*850db82fSStefan Roese * included in all copies or substantial portions of the Software. 36*850db82fSStefan Roese * 37*850db82fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38*850db82fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39*850db82fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40*850db82fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41*850db82fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42*850db82fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43*850db82fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44*850db82fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 45*850db82fSStefan Roese */ 46*850db82fSStefan Roese 47*850db82fSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 48*850db82fSStefan Roese 49*850db82fSStefan Roese/ { 50*850db82fSStefan Roese model = "Marvell Armada 37xx SoC"; 51*850db82fSStefan Roese compatible = "marvell,armada3700"; 52*850db82fSStefan Roese interrupt-parent = <&gic>; 53*850db82fSStefan Roese #address-cells = <2>; 54*850db82fSStefan Roese #size-cells = <2>; 55*850db82fSStefan Roese 56*850db82fSStefan Roese aliases { 57*850db82fSStefan Roese serial0 = &uart0; 58*850db82fSStefan Roese }; 59*850db82fSStefan Roese 60*850db82fSStefan Roese cpus { 61*850db82fSStefan Roese #address-cells = <1>; 62*850db82fSStefan Roese #size-cells = <0>; 63*850db82fSStefan Roese cpu@0 { 64*850db82fSStefan Roese device_type = "cpu"; 65*850db82fSStefan Roese compatible = "arm,cortex-a53", "arm,armv8"; 66*850db82fSStefan Roese reg = <0>; 67*850db82fSStefan Roese enable-method = "psci"; 68*850db82fSStefan Roese }; 69*850db82fSStefan Roese }; 70*850db82fSStefan Roese 71*850db82fSStefan Roese psci { 72*850db82fSStefan Roese compatible = "arm,psci-0.2"; 73*850db82fSStefan Roese method = "smc"; 74*850db82fSStefan Roese }; 75*850db82fSStefan Roese 76*850db82fSStefan Roese timer { 77*850db82fSStefan Roese compatible = "arm,armv8-timer"; 78*850db82fSStefan Roese interrupts = <GIC_PPI 13 79*850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 80*850db82fSStefan Roese <GIC_PPI 14 81*850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82*850db82fSStefan Roese <GIC_PPI 11 83*850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84*850db82fSStefan Roese <GIC_PPI 10 85*850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 86*850db82fSStefan Roese }; 87*850db82fSStefan Roese 88*850db82fSStefan Roese soc { 89*850db82fSStefan Roese compatible = "simple-bus"; 90*850db82fSStefan Roese #address-cells = <2>; 91*850db82fSStefan Roese #size-cells = <2>; 92*850db82fSStefan Roese ranges; 93*850db82fSStefan Roese 94*850db82fSStefan Roese internal-regs { 95*850db82fSStefan Roese #address-cells = <1>; 96*850db82fSStefan Roese #size-cells = <1>; 97*850db82fSStefan Roese compatible = "simple-bus"; 98*850db82fSStefan Roese /* 32M internal register @ 0xd000_0000 */ 99*850db82fSStefan Roese ranges = <0x0 0x0 0xd0000000 0x2000000>; 100*850db82fSStefan Roese 101*850db82fSStefan Roese uart0: serial@12000 { 102*850db82fSStefan Roese compatible = "marvell,armada-3700-uart"; 103*850db82fSStefan Roese reg = <0x12000 0x400>; 104*850db82fSStefan Roese interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 105*850db82fSStefan Roese status = "disabled"; 106*850db82fSStefan Roese }; 107*850db82fSStefan Roese 108*850db82fSStefan Roese usb3: usb@58000 { 109*850db82fSStefan Roese compatible = "marvell,armada3700-xhci", 110*850db82fSStefan Roese "generic-xhci"; 111*850db82fSStefan Roese reg = <0x58000 0x4000>; 112*850db82fSStefan Roese interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 113*850db82fSStefan Roese status = "disabled"; 114*850db82fSStefan Roese }; 115*850db82fSStefan Roese 116*850db82fSStefan Roese xor@60900 { 117*850db82fSStefan Roese compatible = "marvell,armada-3700-xor"; 118*850db82fSStefan Roese reg = <0x60900 0x100 119*850db82fSStefan Roese 0x60b00 0x100>; 120*850db82fSStefan Roese 121*850db82fSStefan Roese xor10 { 122*850db82fSStefan Roese interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 123*850db82fSStefan Roese }; 124*850db82fSStefan Roese xor11 { 125*850db82fSStefan Roese interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 126*850db82fSStefan Roese }; 127*850db82fSStefan Roese }; 128*850db82fSStefan Roese 129*850db82fSStefan Roese sata: sata@e0000 { 130*850db82fSStefan Roese compatible = "marvell,armada-3700-ahci"; 131*850db82fSStefan Roese reg = <0xe0000 0x2000>; 132*850db82fSStefan Roese interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 133*850db82fSStefan Roese status = "disabled"; 134*850db82fSStefan Roese }; 135*850db82fSStefan Roese 136*850db82fSStefan Roese gic: interrupt-controller@1d00000 { 137*850db82fSStefan Roese compatible = "arm,gic-v3"; 138*850db82fSStefan Roese #interrupt-cells = <3>; 139*850db82fSStefan Roese interrupt-controller; 140*850db82fSStefan Roese reg = <0x1d00000 0x10000>, /* GICD */ 141*850db82fSStefan Roese <0x1d40000 0x40000>; /* GICR */ 142*850db82fSStefan Roese }; 143*850db82fSStefan Roese }; 144*850db82fSStefan Roese }; 145*850db82fSStefan Roese}; 146