1850db82fSStefan Roese/* 2850db82fSStefan Roese * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3850db82fSStefan Roese * 4850db82fSStefan Roese * Copyright (C) 2016 Marvell 5850db82fSStefan Roese * 6850db82fSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 7850db82fSStefan Roese * 8850db82fSStefan Roese * This file is dual-licensed: you can use it either under the terms 9850db82fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 10850db82fSStefan Roese * licensing only applies to this file, and not this project as a 11850db82fSStefan Roese * whole. 12850db82fSStefan Roese * 13850db82fSStefan Roese * a) This file is free software; you can redistribute it and/or 14850db82fSStefan Roese * modify it under the terms of the GNU General Public License as 15850db82fSStefan Roese * published by the Free Software Foundation; either version 2 of the 16850db82fSStefan Roese * License, or (at your option) any later version. 17850db82fSStefan Roese * 18850db82fSStefan Roese * This file is distributed in the hope that it will be useful 19850db82fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 20850db82fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21850db82fSStefan Roese * GNU General Public License for more details. 22850db82fSStefan Roese * 23850db82fSStefan Roese * Or, alternatively 24850db82fSStefan Roese * 25850db82fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 26850db82fSStefan Roese * obtaining a copy of this software and associated documentation 27850db82fSStefan Roese * files (the "Software"), to deal in the Software without 28850db82fSStefan Roese * restriction, including without limitation the rights to use 29850db82fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 30850db82fSStefan Roese * sell copies of the Software, and to permit persons to whom the 31850db82fSStefan Roese * Software is furnished to do so, subject to the following 32850db82fSStefan Roese * conditions: 33850db82fSStefan Roese * 34850db82fSStefan Roese * The above copyright notice and this permission notice shall be 35850db82fSStefan Roese * included in all copies or substantial portions of the Software. 36850db82fSStefan Roese * 37850db82fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38850db82fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39850db82fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40850db82fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41850db82fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42850db82fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43850db82fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44850db82fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 45850db82fSStefan Roese */ 46850db82fSStefan Roese 47850db82fSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 4856d53956SStefan Roese#include <dt-bindings/comphy/comphy_data.h> 49850db82fSStefan Roese 50850db82fSStefan Roese/ { 51850db82fSStefan Roese model = "Marvell Armada 37xx SoC"; 52850db82fSStefan Roese compatible = "marvell,armada3700"; 53850db82fSStefan Roese interrupt-parent = <&gic>; 54850db82fSStefan Roese #address-cells = <2>; 55850db82fSStefan Roese #size-cells = <2>; 56850db82fSStefan Roese 57850db82fSStefan Roese aliases { 58850db82fSStefan Roese serial0 = &uart0; 59850db82fSStefan Roese }; 60850db82fSStefan Roese 61850db82fSStefan Roese cpus { 62850db82fSStefan Roese #address-cells = <1>; 63850db82fSStefan Roese #size-cells = <0>; 64850db82fSStefan Roese cpu@0 { 65850db82fSStefan Roese device_type = "cpu"; 66850db82fSStefan Roese compatible = "arm,cortex-a53", "arm,armv8"; 67850db82fSStefan Roese reg = <0>; 68850db82fSStefan Roese enable-method = "psci"; 69850db82fSStefan Roese }; 70850db82fSStefan Roese }; 71850db82fSStefan Roese 72850db82fSStefan Roese psci { 73850db82fSStefan Roese compatible = "arm,psci-0.2"; 74850db82fSStefan Roese method = "smc"; 75850db82fSStefan Roese }; 76850db82fSStefan Roese 77850db82fSStefan Roese timer { 78850db82fSStefan Roese compatible = "arm,armv8-timer"; 79850db82fSStefan Roese interrupts = <GIC_PPI 13 80850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 81850db82fSStefan Roese <GIC_PPI 14 82850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 83850db82fSStefan Roese <GIC_PPI 11 84850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 85850db82fSStefan Roese <GIC_PPI 10 86850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 87850db82fSStefan Roese }; 88850db82fSStefan Roese 89850db82fSStefan Roese soc { 90850db82fSStefan Roese compatible = "simple-bus"; 91850db82fSStefan Roese #address-cells = <2>; 92850db82fSStefan Roese #size-cells = <2>; 93850db82fSStefan Roese ranges; 94850db82fSStefan Roese 95850db82fSStefan Roese internal-regs { 96850db82fSStefan Roese #address-cells = <1>; 97850db82fSStefan Roese #size-cells = <1>; 98850db82fSStefan Roese compatible = "simple-bus"; 99850db82fSStefan Roese /* 32M internal register @ 0xd000_0000 */ 100850db82fSStefan Roese ranges = <0x0 0x0 0xd0000000 0x2000000>; 101850db82fSStefan Roese 102850db82fSStefan Roese uart0: serial@12000 { 103850db82fSStefan Roese compatible = "marvell,armada-3700-uart"; 104850db82fSStefan Roese reg = <0x12000 0x400>; 105850db82fSStefan Roese interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 106850db82fSStefan Roese status = "disabled"; 107850db82fSStefan Roese }; 108850db82fSStefan Roese 109*5cb7b795SGregory CLEMENT pinctrl_nb: pinctrl-nb@13800 { 110*5cb7b795SGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 111*5cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 112*5cb7b795SGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 113*5cb7b795SGregory CLEMENT gpionb: gpionb { 114*5cb7b795SGregory CLEMENT #gpio-cells = <2>; 115*5cb7b795SGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 116*5cb7b795SGregory CLEMENT gpio-controller; 117*5cb7b795SGregory CLEMENT interrupts = 118*5cb7b795SGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 119*5cb7b795SGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 120*5cb7b795SGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 121*5cb7b795SGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 122*5cb7b795SGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 123*5cb7b795SGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 124*5cb7b795SGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 125*5cb7b795SGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 126*5cb7b795SGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 127*5cb7b795SGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 128*5cb7b795SGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 129*5cb7b795SGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 130*5cb7b795SGregory CLEMENT 131*5cb7b795SGregory CLEMENT }; 132*5cb7b795SGregory CLEMENT }; 133*5cb7b795SGregory CLEMENT 134*5cb7b795SGregory CLEMENT pinctrl_sb: pinctrl-sb@18800 { 135*5cb7b795SGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 136*5cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 137*5cb7b795SGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 138*5cb7b795SGregory CLEMENT gpiosb: gpiosb { 139*5cb7b795SGregory CLEMENT #gpio-cells = <2>; 140*5cb7b795SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 29>; 141*5cb7b795SGregory CLEMENT gpio-controller; 142*5cb7b795SGregory CLEMENT interrupts = 143*5cb7b795SGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 144*5cb7b795SGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 145*5cb7b795SGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 146*5cb7b795SGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 147*5cb7b795SGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 148*5cb7b795SGregory CLEMENT }; 149*5cb7b795SGregory CLEMENT }; 150*5cb7b795SGregory CLEMENT 151850db82fSStefan Roese usb3: usb@58000 { 152850db82fSStefan Roese compatible = "marvell,armada3700-xhci", 153850db82fSStefan Roese "generic-xhci"; 154850db82fSStefan Roese reg = <0x58000 0x4000>; 155850db82fSStefan Roese interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 156850db82fSStefan Roese status = "disabled"; 157850db82fSStefan Roese }; 158850db82fSStefan Roese 159f733228aSStefan Roese usb2: usb@5e000 { 160f733228aSStefan Roese compatible = "marvell,armada3700-ehci"; 161f733228aSStefan Roese reg = <0x5e000 0x450>; 162f733228aSStefan Roese status = "disabled"; 163f733228aSStefan Roese }; 164f733228aSStefan Roese 165850db82fSStefan Roese xor@60900 { 166850db82fSStefan Roese compatible = "marvell,armada-3700-xor"; 167850db82fSStefan Roese reg = <0x60900 0x100 168850db82fSStefan Roese 0x60b00 0x100>; 169850db82fSStefan Roese 170850db82fSStefan Roese xor10 { 171850db82fSStefan Roese interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 172850db82fSStefan Roese }; 173850db82fSStefan Roese xor11 { 174850db82fSStefan Roese interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 175850db82fSStefan Roese }; 176850db82fSStefan Roese }; 177850db82fSStefan Roese 178cbe0ece8SStefan Roese sdhci0: sdhci@d0000 { 179cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 180cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 181cbe0ece8SStefan Roese reg = <0xd0000 0x300 182cbe0ece8SStefan Roese 0x1e808 0x4>; 183cbe0ece8SStefan Roese status = "disabled"; 184cbe0ece8SStefan Roese }; 185cbe0ece8SStefan Roese 186cbe0ece8SStefan Roese sdhci1: sdhci@d8000 { 187cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 188cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 189cbe0ece8SStefan Roese reg = <0xd8000 0x300 190cbe0ece8SStefan Roese 0x17808 0x4>; 191cbe0ece8SStefan Roese status = "disabled"; 192cbe0ece8SStefan Roese }; 193cbe0ece8SStefan Roese 194850db82fSStefan Roese sata: sata@e0000 { 195850db82fSStefan Roese compatible = "marvell,armada-3700-ahci"; 196850db82fSStefan Roese reg = <0xe0000 0x2000>; 197850db82fSStefan Roese interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 198850db82fSStefan Roese status = "disabled"; 199850db82fSStefan Roese }; 200850db82fSStefan Roese 201850db82fSStefan Roese gic: interrupt-controller@1d00000 { 202850db82fSStefan Roese compatible = "arm,gic-v3"; 203850db82fSStefan Roese #interrupt-cells = <3>; 204850db82fSStefan Roese interrupt-controller; 205850db82fSStefan Roese reg = <0x1d00000 0x10000>, /* GICD */ 206850db82fSStefan Roese <0x1d40000 0x40000>; /* GICR */ 207850db82fSStefan Roese }; 208cdccf9c1SStefan Roese 2093f84e2e8SStefan Roese eth0: neta@30000 { 2103f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2113f84e2e8SStefan Roese reg = <0x30000 0x20>; 2123f84e2e8SStefan Roese status = "disabled"; 2133f84e2e8SStefan Roese }; 2143f84e2e8SStefan Roese 2153f84e2e8SStefan Roese eth1: neta@40000 { 2163f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2173f84e2e8SStefan Roese reg = <0x40000 0x20>; 2183f84e2e8SStefan Roese status = "disabled"; 2193f84e2e8SStefan Roese }; 2203f84e2e8SStefan Roese 2219e9e63c0SStefan Roese i2c0: i2c@11000 { 2229e9e63c0SStefan Roese compatible = "marvell,armada-3700-i2c"; 2239e9e63c0SStefan Roese reg = <0x11000 0x100>; 2249e9e63c0SStefan Roese status = "disabled"; 2259e9e63c0SStefan Roese }; 2269e9e63c0SStefan Roese 227cdccf9c1SStefan Roese spi0: spi@10600 { 228cdccf9c1SStefan Roese compatible = "marvell,armada-3700-spi"; 229cdccf9c1SStefan Roese reg = <0x10600 0x50>; 230cdccf9c1SStefan Roese #address-cells = <1>; 231cdccf9c1SStefan Roese #size-cells = <0>; 232cdccf9c1SStefan Roese #clock-cells = <0>; 233cdccf9c1SStefan Roese clock-frequency = <160000>; 234cdccf9c1SStefan Roese spi-max-frequency = <40000>; 235cdccf9c1SStefan Roese status = "disabled"; 236cdccf9c1SStefan Roese }; 23756d53956SStefan Roese 238f7cab0f9SKonstantin Porotchkin pinctl0: pinctl@13830 { /* north bridge */ 239f7cab0f9SKonstantin Porotchkin compatible = "marvell,armada-3700-pinctl"; 240f7cab0f9SKonstantin Porotchkin bank-name = "armada-3700-nb"; 241f7cab0f9SKonstantin Porotchkin reg = <0x13830 0x4>; 242f7cab0f9SKonstantin Porotchkin pin-count = <36>; 243f7cab0f9SKonstantin Porotchkin }; 244f7cab0f9SKonstantin Porotchkin 245f7cab0f9SKonstantin Porotchkin pinctl1: pinctl@18830 { /* south bridge */ 246f7cab0f9SKonstantin Porotchkin compatible = "marvell,armada-3700-pinctl"; 247f7cab0f9SKonstantin Porotchkin bank-name = "armada-3700-sb"; 248f7cab0f9SKonstantin Porotchkin reg = <0x18830 0x4>; 249f7cab0f9SKonstantin Porotchkin pin-count = <30>; 250f7cab0f9SKonstantin Porotchkin }; 251f7cab0f9SKonstantin Porotchkin 25256d53956SStefan Roese comphy: comphy@18300 { 25356d53956SStefan Roese compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 25456d53956SStefan Roese reg = <0x18300 0x28>, 25556d53956SStefan Roese <0x1f300 0x3d000>; 25656d53956SStefan Roese mux-bitcount = <1>; 25756d53956SStefan Roese max-lanes = <2>; 25856d53956SStefan Roese }; 259850db82fSStefan Roese }; 260850db82fSStefan Roese }; 261850db82fSStefan Roese}; 262