1850db82fSStefan Roese/* 2850db82fSStefan Roese * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3850db82fSStefan Roese * 4850db82fSStefan Roese * Copyright (C) 2016 Marvell 5850db82fSStefan Roese * 6850db82fSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 7850db82fSStefan Roese * 8850db82fSStefan Roese * This file is dual-licensed: you can use it either under the terms 9850db82fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 10850db82fSStefan Roese * licensing only applies to this file, and not this project as a 11850db82fSStefan Roese * whole. 12850db82fSStefan Roese * 13850db82fSStefan Roese * a) This file is free software; you can redistribute it and/or 14850db82fSStefan Roese * modify it under the terms of the GNU General Public License as 15850db82fSStefan Roese * published by the Free Software Foundation; either version 2 of the 16850db82fSStefan Roese * License, or (at your option) any later version. 17850db82fSStefan Roese * 18850db82fSStefan Roese * This file is distributed in the hope that it will be useful 19850db82fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 20850db82fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21850db82fSStefan Roese * GNU General Public License for more details. 22850db82fSStefan Roese * 23850db82fSStefan Roese * Or, alternatively 24850db82fSStefan Roese * 25850db82fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 26850db82fSStefan Roese * obtaining a copy of this software and associated documentation 27850db82fSStefan Roese * files (the "Software"), to deal in the Software without 28850db82fSStefan Roese * restriction, including without limitation the rights to use 29850db82fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 30850db82fSStefan Roese * sell copies of the Software, and to permit persons to whom the 31850db82fSStefan Roese * Software is furnished to do so, subject to the following 32850db82fSStefan Roese * conditions: 33850db82fSStefan Roese * 34850db82fSStefan Roese * The above copyright notice and this permission notice shall be 35850db82fSStefan Roese * included in all copies or substantial portions of the Software. 36850db82fSStefan Roese * 37850db82fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38850db82fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39850db82fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40850db82fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41850db82fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42850db82fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43850db82fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44850db82fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 45850db82fSStefan Roese */ 46850db82fSStefan Roese 47850db82fSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 4856d53956SStefan Roese#include <dt-bindings/comphy/comphy_data.h> 49d13d8ba1SKen Ma#include <dt-bindings/gpio/gpio.h> 50850db82fSStefan Roese 51850db82fSStefan Roese/ { 52850db82fSStefan Roese model = "Marvell Armada 37xx SoC"; 53850db82fSStefan Roese compatible = "marvell,armada3700"; 54850db82fSStefan Roese interrupt-parent = <&gic>; 55850db82fSStefan Roese #address-cells = <2>; 56850db82fSStefan Roese #size-cells = <2>; 57850db82fSStefan Roese 58850db82fSStefan Roese aliases { 59850db82fSStefan Roese serial0 = &uart0; 60850db82fSStefan Roese }; 61850db82fSStefan Roese 62850db82fSStefan Roese cpus { 63850db82fSStefan Roese #address-cells = <1>; 64850db82fSStefan Roese #size-cells = <0>; 65850db82fSStefan Roese cpu@0 { 66850db82fSStefan Roese device_type = "cpu"; 67850db82fSStefan Roese compatible = "arm,cortex-a53", "arm,armv8"; 68850db82fSStefan Roese reg = <0>; 69850db82fSStefan Roese enable-method = "psci"; 70850db82fSStefan Roese }; 71850db82fSStefan Roese }; 72850db82fSStefan Roese 73850db82fSStefan Roese psci { 74850db82fSStefan Roese compatible = "arm,psci-0.2"; 75850db82fSStefan Roese method = "smc"; 76850db82fSStefan Roese }; 77850db82fSStefan Roese 78850db82fSStefan Roese timer { 79850db82fSStefan Roese compatible = "arm,armv8-timer"; 80850db82fSStefan Roese interrupts = <GIC_PPI 13 81850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82850db82fSStefan Roese <GIC_PPI 14 83850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84850db82fSStefan Roese <GIC_PPI 11 85850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 86850db82fSStefan Roese <GIC_PPI 10 87850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 88850db82fSStefan Roese }; 89850db82fSStefan Roese 90850db82fSStefan Roese soc { 91850db82fSStefan Roese compatible = "simple-bus"; 92850db82fSStefan Roese #address-cells = <2>; 93850db82fSStefan Roese #size-cells = <2>; 94850db82fSStefan Roese ranges; 95850db82fSStefan Roese 96850db82fSStefan Roese internal-regs { 97850db82fSStefan Roese #address-cells = <1>; 98850db82fSStefan Roese #size-cells = <1>; 99850db82fSStefan Roese compatible = "simple-bus"; 100850db82fSStefan Roese /* 32M internal register @ 0xd000_0000 */ 101850db82fSStefan Roese ranges = <0x0 0x0 0xd0000000 0x2000000>; 102850db82fSStefan Roese 103850db82fSStefan Roese uart0: serial@12000 { 104850db82fSStefan Roese compatible = "marvell,armada-3700-uart"; 105850db82fSStefan Roese reg = <0x12000 0x400>; 106850db82fSStefan Roese interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 107850db82fSStefan Roese status = "disabled"; 108850db82fSStefan Roese }; 109850db82fSStefan Roese 1105cb7b795SGregory CLEMENT pinctrl_nb: pinctrl-nb@13800 { 1115cb7b795SGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 1125cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 1135cb7b795SGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 1145cb7b795SGregory CLEMENT gpionb: gpionb { 1155cb7b795SGregory CLEMENT #gpio-cells = <2>; 1165cb7b795SGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 1175cb7b795SGregory CLEMENT gpio-controller; 1185cb7b795SGregory CLEMENT interrupts = 1195cb7b795SGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1205cb7b795SGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1215cb7b795SGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1225cb7b795SGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1235cb7b795SGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1245cb7b795SGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1255cb7b795SGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1265cb7b795SGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1275cb7b795SGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1285cb7b795SGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1295cb7b795SGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1305cb7b795SGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1315cb7b795SGregory CLEMENT 1325cb7b795SGregory CLEMENT }; 133045504bbSGregory CLEMENT 134045504bbSGregory CLEMENT spi_quad_pins: spi-quad-pins { 135045504bbSGregory CLEMENT groups = "spi_quad"; 136045504bbSGregory CLEMENT function = "spi"; 137045504bbSGregory CLEMENT }; 138045504bbSGregory CLEMENT 139045504bbSGregory CLEMENT i2c1_pins: i2c1-pins { 140045504bbSGregory CLEMENT groups = "i2c1"; 141045504bbSGregory CLEMENT function = "i2c"; 142045504bbSGregory CLEMENT }; 143045504bbSGregory CLEMENT 144045504bbSGregory CLEMENT i2c2_pins: i2c2-pins { 145045504bbSGregory CLEMENT groups = "i2c2"; 146045504bbSGregory CLEMENT function = "i2c"; 147045504bbSGregory CLEMENT }; 148045504bbSGregory CLEMENT 149045504bbSGregory CLEMENT uart1_pins: uart1-pins { 150045504bbSGregory CLEMENT groups = "uart1"; 151045504bbSGregory CLEMENT function = "uart"; 152045504bbSGregory CLEMENT }; 153045504bbSGregory CLEMENT 154045504bbSGregory CLEMENT uart2_pins: uart2-pins { 155045504bbSGregory CLEMENT groups = "uart2"; 156045504bbSGregory CLEMENT function = "uart"; 157045504bbSGregory CLEMENT }; 158*4382e53eSKen Ma 159*4382e53eSKen Ma mmc_pins: mmc-pins { 160*4382e53eSKen Ma groups = "emmc_nb"; 161*4382e53eSKen Ma function = "emmc"; 162*4382e53eSKen Ma }; 1635cb7b795SGregory CLEMENT }; 1645cb7b795SGregory CLEMENT 1655cb7b795SGregory CLEMENT pinctrl_sb: pinctrl-sb@18800 { 1665cb7b795SGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 1675cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 1685cb7b795SGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 1695cb7b795SGregory CLEMENT gpiosb: gpiosb { 1705cb7b795SGregory CLEMENT #gpio-cells = <2>; 1715cb7b795SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 29>; 1725cb7b795SGregory CLEMENT gpio-controller; 1735cb7b795SGregory CLEMENT interrupts = 1745cb7b795SGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1755cb7b795SGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1765cb7b795SGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1775cb7b795SGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1785cb7b795SGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1795cb7b795SGregory CLEMENT }; 180045504bbSGregory CLEMENT 181045504bbSGregory CLEMENT rgmii_pins: mii-pins { 182045504bbSGregory CLEMENT groups = "rgmii"; 183045504bbSGregory CLEMENT function = "mii"; 184045504bbSGregory CLEMENT }; 185045504bbSGregory CLEMENT 186*4382e53eSKen Ma sdio_pins: sdio-pins { 187*4382e53eSKen Ma groups = "sdio_sb"; 188*4382e53eSKen Ma function = "sdio"; 189*4382e53eSKen Ma }; 190*4382e53eSKen Ma 191*4382e53eSKen Ma pcie_pins: pcie-pins { 192*4382e53eSKen Ma groups = "pcie1"; 193*4382e53eSKen Ma function = "pcie"; 194*4382e53eSKen Ma }; 1955cb7b795SGregory CLEMENT }; 1965cb7b795SGregory CLEMENT 197850db82fSStefan Roese usb3: usb@58000 { 198850db82fSStefan Roese compatible = "marvell,armada3700-xhci", 199850db82fSStefan Roese "generic-xhci"; 200850db82fSStefan Roese reg = <0x58000 0x4000>; 201850db82fSStefan Roese interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 202850db82fSStefan Roese status = "disabled"; 203850db82fSStefan Roese }; 204850db82fSStefan Roese 205f733228aSStefan Roese usb2: usb@5e000 { 206f733228aSStefan Roese compatible = "marvell,armada3700-ehci"; 207f733228aSStefan Roese reg = <0x5e000 0x450>; 208f733228aSStefan Roese status = "disabled"; 209f733228aSStefan Roese }; 210f733228aSStefan Roese 211850db82fSStefan Roese xor@60900 { 212850db82fSStefan Roese compatible = "marvell,armada-3700-xor"; 213850db82fSStefan Roese reg = <0x60900 0x100 214850db82fSStefan Roese 0x60b00 0x100>; 215850db82fSStefan Roese 216850db82fSStefan Roese xor10 { 217850db82fSStefan Roese interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 218850db82fSStefan Roese }; 219850db82fSStefan Roese xor11 { 220850db82fSStefan Roese interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 221850db82fSStefan Roese }; 222850db82fSStefan Roese }; 223850db82fSStefan Roese 224cbe0ece8SStefan Roese sdhci0: sdhci@d0000 { 225cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 226cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 227cbe0ece8SStefan Roese reg = <0xd0000 0x300 228cbe0ece8SStefan Roese 0x1e808 0x4>; 229cbe0ece8SStefan Roese status = "disabled"; 230cbe0ece8SStefan Roese }; 231cbe0ece8SStefan Roese 232cbe0ece8SStefan Roese sdhci1: sdhci@d8000 { 233cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 234cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 235cbe0ece8SStefan Roese reg = <0xd8000 0x300 236cbe0ece8SStefan Roese 0x17808 0x4>; 237cbe0ece8SStefan Roese status = "disabled"; 238cbe0ece8SStefan Roese }; 239cbe0ece8SStefan Roese 240850db82fSStefan Roese sata: sata@e0000 { 241850db82fSStefan Roese compatible = "marvell,armada-3700-ahci"; 242850db82fSStefan Roese reg = <0xe0000 0x2000>; 243850db82fSStefan Roese interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 244850db82fSStefan Roese status = "disabled"; 245850db82fSStefan Roese }; 246850db82fSStefan Roese 247850db82fSStefan Roese gic: interrupt-controller@1d00000 { 248850db82fSStefan Roese compatible = "arm,gic-v3"; 249850db82fSStefan Roese #interrupt-cells = <3>; 250850db82fSStefan Roese interrupt-controller; 251850db82fSStefan Roese reg = <0x1d00000 0x10000>, /* GICD */ 252850db82fSStefan Roese <0x1d40000 0x40000>; /* GICR */ 253850db82fSStefan Roese }; 254cdccf9c1SStefan Roese 2553f84e2e8SStefan Roese eth0: neta@30000 { 2563f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2573f84e2e8SStefan Roese reg = <0x30000 0x20>; 2583f84e2e8SStefan Roese status = "disabled"; 2593f84e2e8SStefan Roese }; 2603f84e2e8SStefan Roese 2613f84e2e8SStefan Roese eth1: neta@40000 { 2623f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2633f84e2e8SStefan Roese reg = <0x40000 0x20>; 2643f84e2e8SStefan Roese status = "disabled"; 2653f84e2e8SStefan Roese }; 2663f84e2e8SStefan Roese 2679e9e63c0SStefan Roese i2c0: i2c@11000 { 2689e9e63c0SStefan Roese compatible = "marvell,armada-3700-i2c"; 2699e9e63c0SStefan Roese reg = <0x11000 0x100>; 2709e9e63c0SStefan Roese status = "disabled"; 2719e9e63c0SStefan Roese }; 2729e9e63c0SStefan Roese 273cdccf9c1SStefan Roese spi0: spi@10600 { 274cdccf9c1SStefan Roese compatible = "marvell,armada-3700-spi"; 275cdccf9c1SStefan Roese reg = <0x10600 0x50>; 276cdccf9c1SStefan Roese #address-cells = <1>; 277cdccf9c1SStefan Roese #size-cells = <0>; 278cdccf9c1SStefan Roese #clock-cells = <0>; 279cdccf9c1SStefan Roese clock-frequency = <160000>; 280cdccf9c1SStefan Roese spi-max-frequency = <40000>; 281cdccf9c1SStefan Roese status = "disabled"; 282cdccf9c1SStefan Roese }; 28356d53956SStefan Roese 284f7cab0f9SKonstantin Porotchkin pinctl0: pinctl@13830 { /* north bridge */ 285f7cab0f9SKonstantin Porotchkin compatible = "marvell,armada-3700-pinctl"; 286f7cab0f9SKonstantin Porotchkin bank-name = "armada-3700-nb"; 287f7cab0f9SKonstantin Porotchkin reg = <0x13830 0x4>; 288f7cab0f9SKonstantin Porotchkin pin-count = <36>; 289f7cab0f9SKonstantin Porotchkin }; 290f7cab0f9SKonstantin Porotchkin 291f7cab0f9SKonstantin Porotchkin pinctl1: pinctl@18830 { /* south bridge */ 292f7cab0f9SKonstantin Porotchkin compatible = "marvell,armada-3700-pinctl"; 293f7cab0f9SKonstantin Porotchkin bank-name = "armada-3700-sb"; 294f7cab0f9SKonstantin Porotchkin reg = <0x18830 0x4>; 295f7cab0f9SKonstantin Porotchkin pin-count = <30>; 296f7cab0f9SKonstantin Porotchkin }; 297f7cab0f9SKonstantin Porotchkin 29856d53956SStefan Roese comphy: comphy@18300 { 29956d53956SStefan Roese compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 30056d53956SStefan Roese reg = <0x18300 0x28>, 30156d53956SStefan Roese <0x1f300 0x3d000>; 30256d53956SStefan Roese mux-bitcount = <1>; 30356d53956SStefan Roese max-lanes = <2>; 30456d53956SStefan Roese }; 305850db82fSStefan Roese }; 306850db82fSStefan Roese }; 307850db82fSStefan Roese}; 308