1850db82fSStefan Roese/* 2850db82fSStefan Roese * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3850db82fSStefan Roese * 4850db82fSStefan Roese * Copyright (C) 2016 Marvell 5850db82fSStefan Roese * 6850db82fSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 7850db82fSStefan Roese * 8850db82fSStefan Roese * This file is dual-licensed: you can use it either under the terms 9850db82fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 10850db82fSStefan Roese * licensing only applies to this file, and not this project as a 11850db82fSStefan Roese * whole. 12850db82fSStefan Roese * 13850db82fSStefan Roese * a) This file is free software; you can redistribute it and/or 14850db82fSStefan Roese * modify it under the terms of the GNU General Public License as 15850db82fSStefan Roese * published by the Free Software Foundation; either version 2 of the 16850db82fSStefan Roese * License, or (at your option) any later version. 17850db82fSStefan Roese * 18850db82fSStefan Roese * This file is distributed in the hope that it will be useful 19850db82fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 20850db82fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21850db82fSStefan Roese * GNU General Public License for more details. 22850db82fSStefan Roese * 23850db82fSStefan Roese * Or, alternatively 24850db82fSStefan Roese * 25850db82fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 26850db82fSStefan Roese * obtaining a copy of this software and associated documentation 27850db82fSStefan Roese * files (the "Software"), to deal in the Software without 28850db82fSStefan Roese * restriction, including without limitation the rights to use 29850db82fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 30850db82fSStefan Roese * sell copies of the Software, and to permit persons to whom the 31850db82fSStefan Roese * Software is furnished to do so, subject to the following 32850db82fSStefan Roese * conditions: 33850db82fSStefan Roese * 34850db82fSStefan Roese * The above copyright notice and this permission notice shall be 35850db82fSStefan Roese * included in all copies or substantial portions of the Software. 36850db82fSStefan Roese * 37850db82fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38850db82fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39850db82fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40850db82fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41850db82fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42850db82fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43850db82fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44850db82fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 45850db82fSStefan Roese */ 46850db82fSStefan Roese 47850db82fSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 48850db82fSStefan Roese 49850db82fSStefan Roese/ { 50850db82fSStefan Roese model = "Marvell Armada 37xx SoC"; 51850db82fSStefan Roese compatible = "marvell,armada3700"; 52850db82fSStefan Roese interrupt-parent = <&gic>; 53850db82fSStefan Roese #address-cells = <2>; 54850db82fSStefan Roese #size-cells = <2>; 55850db82fSStefan Roese 56850db82fSStefan Roese aliases { 57850db82fSStefan Roese serial0 = &uart0; 58850db82fSStefan Roese }; 59850db82fSStefan Roese 60850db82fSStefan Roese cpus { 61850db82fSStefan Roese #address-cells = <1>; 62850db82fSStefan Roese #size-cells = <0>; 63850db82fSStefan Roese cpu@0 { 64850db82fSStefan Roese device_type = "cpu"; 65850db82fSStefan Roese compatible = "arm,cortex-a53", "arm,armv8"; 66850db82fSStefan Roese reg = <0>; 67850db82fSStefan Roese enable-method = "psci"; 68850db82fSStefan Roese }; 69850db82fSStefan Roese }; 70850db82fSStefan Roese 71850db82fSStefan Roese psci { 72850db82fSStefan Roese compatible = "arm,psci-0.2"; 73850db82fSStefan Roese method = "smc"; 74850db82fSStefan Roese }; 75850db82fSStefan Roese 76850db82fSStefan Roese timer { 77850db82fSStefan Roese compatible = "arm,armv8-timer"; 78850db82fSStefan Roese interrupts = <GIC_PPI 13 79850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 80850db82fSStefan Roese <GIC_PPI 14 81850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82850db82fSStefan Roese <GIC_PPI 11 83850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84850db82fSStefan Roese <GIC_PPI 10 85850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 86850db82fSStefan Roese }; 87850db82fSStefan Roese 88850db82fSStefan Roese soc { 89850db82fSStefan Roese compatible = "simple-bus"; 90850db82fSStefan Roese #address-cells = <2>; 91850db82fSStefan Roese #size-cells = <2>; 92850db82fSStefan Roese ranges; 93850db82fSStefan Roese 94850db82fSStefan Roese internal-regs { 95850db82fSStefan Roese #address-cells = <1>; 96850db82fSStefan Roese #size-cells = <1>; 97850db82fSStefan Roese compatible = "simple-bus"; 98850db82fSStefan Roese /* 32M internal register @ 0xd000_0000 */ 99850db82fSStefan Roese ranges = <0x0 0x0 0xd0000000 0x2000000>; 100850db82fSStefan Roese 101850db82fSStefan Roese uart0: serial@12000 { 102850db82fSStefan Roese compatible = "marvell,armada-3700-uart"; 103850db82fSStefan Roese reg = <0x12000 0x400>; 104850db82fSStefan Roese interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 105850db82fSStefan Roese status = "disabled"; 106850db82fSStefan Roese }; 107850db82fSStefan Roese 108850db82fSStefan Roese usb3: usb@58000 { 109850db82fSStefan Roese compatible = "marvell,armada3700-xhci", 110850db82fSStefan Roese "generic-xhci"; 111850db82fSStefan Roese reg = <0x58000 0x4000>; 112850db82fSStefan Roese interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 113850db82fSStefan Roese status = "disabled"; 114850db82fSStefan Roese }; 115850db82fSStefan Roese 116850db82fSStefan Roese xor@60900 { 117850db82fSStefan Roese compatible = "marvell,armada-3700-xor"; 118850db82fSStefan Roese reg = <0x60900 0x100 119850db82fSStefan Roese 0x60b00 0x100>; 120850db82fSStefan Roese 121850db82fSStefan Roese xor10 { 122850db82fSStefan Roese interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 123850db82fSStefan Roese }; 124850db82fSStefan Roese xor11 { 125850db82fSStefan Roese interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 126850db82fSStefan Roese }; 127850db82fSStefan Roese }; 128850db82fSStefan Roese 129850db82fSStefan Roese sata: sata@e0000 { 130850db82fSStefan Roese compatible = "marvell,armada-3700-ahci"; 131850db82fSStefan Roese reg = <0xe0000 0x2000>; 132850db82fSStefan Roese interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 133850db82fSStefan Roese status = "disabled"; 134850db82fSStefan Roese }; 135850db82fSStefan Roese 136850db82fSStefan Roese gic: interrupt-controller@1d00000 { 137850db82fSStefan Roese compatible = "arm,gic-v3"; 138850db82fSStefan Roese #interrupt-cells = <3>; 139850db82fSStefan Roese interrupt-controller; 140850db82fSStefan Roese reg = <0x1d00000 0x10000>, /* GICD */ 141850db82fSStefan Roese <0x1d40000 0x40000>; /* GICR */ 142850db82fSStefan Roese }; 143cdccf9c1SStefan Roese 144*3f84e2e8SStefan Roese eth0: neta@30000 { 145*3f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 146*3f84e2e8SStefan Roese reg = <0x30000 0x20>; 147*3f84e2e8SStefan Roese status = "disabled"; 148*3f84e2e8SStefan Roese }; 149*3f84e2e8SStefan Roese 150*3f84e2e8SStefan Roese eth1: neta@40000 { 151*3f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 152*3f84e2e8SStefan Roese reg = <0x40000 0x20>; 153*3f84e2e8SStefan Roese status = "disabled"; 154*3f84e2e8SStefan Roese }; 155*3f84e2e8SStefan Roese 156cdccf9c1SStefan Roese spi0: spi@10600 { 157cdccf9c1SStefan Roese compatible = "marvell,armada-3700-spi"; 158cdccf9c1SStefan Roese reg = <0x10600 0x50>; 159cdccf9c1SStefan Roese #address-cells = <1>; 160cdccf9c1SStefan Roese #size-cells = <0>; 161cdccf9c1SStefan Roese #clock-cells = <0>; 162cdccf9c1SStefan Roese clock-frequency = <160000>; 163cdccf9c1SStefan Roese spi-max-frequency = <40000>; 164cdccf9c1SStefan Roese status = "disabled"; 165cdccf9c1SStefan Roese }; 166850db82fSStefan Roese }; 167850db82fSStefan Roese }; 168850db82fSStefan Roese}; 169