1850db82fSStefan Roese/* 2850db82fSStefan Roese * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3850db82fSStefan Roese * 4850db82fSStefan Roese * Copyright (C) 2016 Marvell 5850db82fSStefan Roese * 6850db82fSStefan Roese * Gregory CLEMENT <gregory.clement@free-electrons.com> 7850db82fSStefan Roese * 8850db82fSStefan Roese * This file is dual-licensed: you can use it either under the terms 9850db82fSStefan Roese * of the GPL or the X11 license, at your option. Note that this dual 10850db82fSStefan Roese * licensing only applies to this file, and not this project as a 11850db82fSStefan Roese * whole. 12850db82fSStefan Roese * 13850db82fSStefan Roese * a) This file is free software; you can redistribute it and/or 14850db82fSStefan Roese * modify it under the terms of the GNU General Public License as 15850db82fSStefan Roese * published by the Free Software Foundation; either version 2 of the 16850db82fSStefan Roese * License, or (at your option) any later version. 17850db82fSStefan Roese * 18850db82fSStefan Roese * This file is distributed in the hope that it will be useful 19850db82fSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 20850db82fSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21850db82fSStefan Roese * GNU General Public License for more details. 22850db82fSStefan Roese * 23850db82fSStefan Roese * Or, alternatively 24850db82fSStefan Roese * 25850db82fSStefan Roese * b) Permission is hereby granted, free of charge, to any person 26850db82fSStefan Roese * obtaining a copy of this software and associated documentation 27850db82fSStefan Roese * files (the "Software"), to deal in the Software without 28850db82fSStefan Roese * restriction, including without limitation the rights to use 29850db82fSStefan Roese * copy, modify, merge, publish, distribute, sublicense, and/or 30850db82fSStefan Roese * sell copies of the Software, and to permit persons to whom the 31850db82fSStefan Roese * Software is furnished to do so, subject to the following 32850db82fSStefan Roese * conditions: 33850db82fSStefan Roese * 34850db82fSStefan Roese * The above copyright notice and this permission notice shall be 35850db82fSStefan Roese * included in all copies or substantial portions of the Software. 36850db82fSStefan Roese * 37850db82fSStefan Roese * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 38850db82fSStefan Roese * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39850db82fSStefan Roese * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40850db82fSStefan Roese * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 41850db82fSStefan Roese * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 42850db82fSStefan Roese * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43850db82fSStefan Roese * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44850db82fSStefan Roese * OTHER DEALINGS IN THE SOFTWARE. 45850db82fSStefan Roese */ 46850db82fSStefan Roese 47850db82fSStefan Roese#include <dt-bindings/interrupt-controller/arm-gic.h> 4856d53956SStefan Roese#include <dt-bindings/comphy/comphy_data.h> 49850db82fSStefan Roese 50850db82fSStefan Roese/ { 51850db82fSStefan Roese model = "Marvell Armada 37xx SoC"; 52850db82fSStefan Roese compatible = "marvell,armada3700"; 53850db82fSStefan Roese interrupt-parent = <&gic>; 54850db82fSStefan Roese #address-cells = <2>; 55850db82fSStefan Roese #size-cells = <2>; 56850db82fSStefan Roese 57850db82fSStefan Roese aliases { 58850db82fSStefan Roese serial0 = &uart0; 59850db82fSStefan Roese }; 60850db82fSStefan Roese 61850db82fSStefan Roese cpus { 62850db82fSStefan Roese #address-cells = <1>; 63850db82fSStefan Roese #size-cells = <0>; 64850db82fSStefan Roese cpu@0 { 65850db82fSStefan Roese device_type = "cpu"; 66850db82fSStefan Roese compatible = "arm,cortex-a53", "arm,armv8"; 67850db82fSStefan Roese reg = <0>; 68850db82fSStefan Roese enable-method = "psci"; 69850db82fSStefan Roese }; 70850db82fSStefan Roese }; 71850db82fSStefan Roese 72850db82fSStefan Roese psci { 73850db82fSStefan Roese compatible = "arm,psci-0.2"; 74850db82fSStefan Roese method = "smc"; 75850db82fSStefan Roese }; 76850db82fSStefan Roese 77850db82fSStefan Roese timer { 78850db82fSStefan Roese compatible = "arm,armv8-timer"; 79850db82fSStefan Roese interrupts = <GIC_PPI 13 80850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 81850db82fSStefan Roese <GIC_PPI 14 82850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 83850db82fSStefan Roese <GIC_PPI 11 84850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 85850db82fSStefan Roese <GIC_PPI 10 86850db82fSStefan Roese (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 87850db82fSStefan Roese }; 88850db82fSStefan Roese 89850db82fSStefan Roese soc { 90850db82fSStefan Roese compatible = "simple-bus"; 91850db82fSStefan Roese #address-cells = <2>; 92850db82fSStefan Roese #size-cells = <2>; 93850db82fSStefan Roese ranges; 94850db82fSStefan Roese 95850db82fSStefan Roese internal-regs { 96850db82fSStefan Roese #address-cells = <1>; 97850db82fSStefan Roese #size-cells = <1>; 98850db82fSStefan Roese compatible = "simple-bus"; 99850db82fSStefan Roese /* 32M internal register @ 0xd000_0000 */ 100850db82fSStefan Roese ranges = <0x0 0x0 0xd0000000 0x2000000>; 101850db82fSStefan Roese 102850db82fSStefan Roese uart0: serial@12000 { 103850db82fSStefan Roese compatible = "marvell,armada-3700-uart"; 104850db82fSStefan Roese reg = <0x12000 0x400>; 105850db82fSStefan Roese interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 106850db82fSStefan Roese status = "disabled"; 107850db82fSStefan Roese }; 108850db82fSStefan Roese 1095cb7b795SGregory CLEMENT pinctrl_nb: pinctrl-nb@13800 { 1105cb7b795SGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 1115cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 1125cb7b795SGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 1135cb7b795SGregory CLEMENT gpionb: gpionb { 1145cb7b795SGregory CLEMENT #gpio-cells = <2>; 1155cb7b795SGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 1165cb7b795SGregory CLEMENT gpio-controller; 1175cb7b795SGregory CLEMENT interrupts = 1185cb7b795SGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1195cb7b795SGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1205cb7b795SGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1215cb7b795SGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1225cb7b795SGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1235cb7b795SGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1245cb7b795SGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1255cb7b795SGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1265cb7b795SGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1275cb7b795SGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1285cb7b795SGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1295cb7b795SGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1305cb7b795SGregory CLEMENT 1315cb7b795SGregory CLEMENT }; 132*045504bbSGregory CLEMENT 133*045504bbSGregory CLEMENT spi_quad_pins: spi-quad-pins { 134*045504bbSGregory CLEMENT groups = "spi_quad"; 135*045504bbSGregory CLEMENT function = "spi"; 136*045504bbSGregory CLEMENT }; 137*045504bbSGregory CLEMENT 138*045504bbSGregory CLEMENT i2c1_pins: i2c1-pins { 139*045504bbSGregory CLEMENT groups = "i2c1"; 140*045504bbSGregory CLEMENT function = "i2c"; 141*045504bbSGregory CLEMENT }; 142*045504bbSGregory CLEMENT 143*045504bbSGregory CLEMENT i2c2_pins: i2c2-pins { 144*045504bbSGregory CLEMENT groups = "i2c2"; 145*045504bbSGregory CLEMENT function = "i2c"; 146*045504bbSGregory CLEMENT }; 147*045504bbSGregory CLEMENT 148*045504bbSGregory CLEMENT uart1_pins: uart1-pins { 149*045504bbSGregory CLEMENT groups = "uart1"; 150*045504bbSGregory CLEMENT function = "uart"; 151*045504bbSGregory CLEMENT }; 152*045504bbSGregory CLEMENT 153*045504bbSGregory CLEMENT uart2_pins: uart2-pins { 154*045504bbSGregory CLEMENT groups = "uart2"; 155*045504bbSGregory CLEMENT function = "uart"; 156*045504bbSGregory CLEMENT }; 1575cb7b795SGregory CLEMENT }; 1585cb7b795SGregory CLEMENT 1595cb7b795SGregory CLEMENT pinctrl_sb: pinctrl-sb@18800 { 1605cb7b795SGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 1615cb7b795SGregory CLEMENT "syscon", "simple-mfd"; 1625cb7b795SGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 1635cb7b795SGregory CLEMENT gpiosb: gpiosb { 1645cb7b795SGregory CLEMENT #gpio-cells = <2>; 1655cb7b795SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 29>; 1665cb7b795SGregory CLEMENT gpio-controller; 1675cb7b795SGregory CLEMENT interrupts = 1685cb7b795SGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1695cb7b795SGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1705cb7b795SGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1715cb7b795SGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1725cb7b795SGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1735cb7b795SGregory CLEMENT }; 174*045504bbSGregory CLEMENT 175*045504bbSGregory CLEMENT rgmii_pins: mii-pins { 176*045504bbSGregory CLEMENT groups = "rgmii"; 177*045504bbSGregory CLEMENT function = "mii"; 178*045504bbSGregory CLEMENT }; 179*045504bbSGregory CLEMENT 1805cb7b795SGregory CLEMENT }; 1815cb7b795SGregory CLEMENT 182850db82fSStefan Roese usb3: usb@58000 { 183850db82fSStefan Roese compatible = "marvell,armada3700-xhci", 184850db82fSStefan Roese "generic-xhci"; 185850db82fSStefan Roese reg = <0x58000 0x4000>; 186850db82fSStefan Roese interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 187850db82fSStefan Roese status = "disabled"; 188850db82fSStefan Roese }; 189850db82fSStefan Roese 190f733228aSStefan Roese usb2: usb@5e000 { 191f733228aSStefan Roese compatible = "marvell,armada3700-ehci"; 192f733228aSStefan Roese reg = <0x5e000 0x450>; 193f733228aSStefan Roese status = "disabled"; 194f733228aSStefan Roese }; 195f733228aSStefan Roese 196850db82fSStefan Roese xor@60900 { 197850db82fSStefan Roese compatible = "marvell,armada-3700-xor"; 198850db82fSStefan Roese reg = <0x60900 0x100 199850db82fSStefan Roese 0x60b00 0x100>; 200850db82fSStefan Roese 201850db82fSStefan Roese xor10 { 202850db82fSStefan Roese interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 203850db82fSStefan Roese }; 204850db82fSStefan Roese xor11 { 205850db82fSStefan Roese interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 206850db82fSStefan Roese }; 207850db82fSStefan Roese }; 208850db82fSStefan Roese 209cbe0ece8SStefan Roese sdhci0: sdhci@d0000 { 210cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 211cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 212cbe0ece8SStefan Roese reg = <0xd0000 0x300 213cbe0ece8SStefan Roese 0x1e808 0x4>; 214cbe0ece8SStefan Roese status = "disabled"; 215cbe0ece8SStefan Roese }; 216cbe0ece8SStefan Roese 217cbe0ece8SStefan Roese sdhci1: sdhci@d8000 { 218cbe0ece8SStefan Roese compatible = "marvell,armada-3700-sdhci", 219cbe0ece8SStefan Roese "marvell,sdhci-xenon"; 220cbe0ece8SStefan Roese reg = <0xd8000 0x300 221cbe0ece8SStefan Roese 0x17808 0x4>; 222cbe0ece8SStefan Roese status = "disabled"; 223cbe0ece8SStefan Roese }; 224cbe0ece8SStefan Roese 225850db82fSStefan Roese sata: sata@e0000 { 226850db82fSStefan Roese compatible = "marvell,armada-3700-ahci"; 227850db82fSStefan Roese reg = <0xe0000 0x2000>; 228850db82fSStefan Roese interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 229850db82fSStefan Roese status = "disabled"; 230850db82fSStefan Roese }; 231850db82fSStefan Roese 232850db82fSStefan Roese gic: interrupt-controller@1d00000 { 233850db82fSStefan Roese compatible = "arm,gic-v3"; 234850db82fSStefan Roese #interrupt-cells = <3>; 235850db82fSStefan Roese interrupt-controller; 236850db82fSStefan Roese reg = <0x1d00000 0x10000>, /* GICD */ 237850db82fSStefan Roese <0x1d40000 0x40000>; /* GICR */ 238850db82fSStefan Roese }; 239cdccf9c1SStefan Roese 2403f84e2e8SStefan Roese eth0: neta@30000 { 2413f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2423f84e2e8SStefan Roese reg = <0x30000 0x20>; 2433f84e2e8SStefan Roese status = "disabled"; 2443f84e2e8SStefan Roese }; 2453f84e2e8SStefan Roese 2463f84e2e8SStefan Roese eth1: neta@40000 { 2473f84e2e8SStefan Roese compatible = "marvell,armada-3700-neta"; 2483f84e2e8SStefan Roese reg = <0x40000 0x20>; 2493f84e2e8SStefan Roese status = "disabled"; 2503f84e2e8SStefan Roese }; 2513f84e2e8SStefan Roese 2529e9e63c0SStefan Roese i2c0: i2c@11000 { 2539e9e63c0SStefan Roese compatible = "marvell,armada-3700-i2c"; 2549e9e63c0SStefan Roese reg = <0x11000 0x100>; 2559e9e63c0SStefan Roese status = "disabled"; 2569e9e63c0SStefan Roese }; 2579e9e63c0SStefan Roese 258cdccf9c1SStefan Roese spi0: spi@10600 { 259cdccf9c1SStefan Roese compatible = "marvell,armada-3700-spi"; 260cdccf9c1SStefan Roese reg = <0x10600 0x50>; 261cdccf9c1SStefan Roese #address-cells = <1>; 262cdccf9c1SStefan Roese #size-cells = <0>; 263cdccf9c1SStefan Roese #clock-cells = <0>; 264cdccf9c1SStefan Roese clock-frequency = <160000>; 265cdccf9c1SStefan Roese spi-max-frequency = <40000>; 266cdccf9c1SStefan Roese status = "disabled"; 267cdccf9c1SStefan Roese }; 26856d53956SStefan Roese 269f7cab0f9SKonstantin Porotchkin pinctl0: pinctl@13830 { /* north bridge */ 270f7cab0f9SKonstantin Porotchkin compatible = "marvell,armada-3700-pinctl"; 271f7cab0f9SKonstantin Porotchkin bank-name = "armada-3700-nb"; 272f7cab0f9SKonstantin Porotchkin reg = <0x13830 0x4>; 273f7cab0f9SKonstantin Porotchkin pin-count = <36>; 274f7cab0f9SKonstantin Porotchkin }; 275f7cab0f9SKonstantin Porotchkin 276f7cab0f9SKonstantin Porotchkin pinctl1: pinctl@18830 { /* south bridge */ 277f7cab0f9SKonstantin Porotchkin compatible = "marvell,armada-3700-pinctl"; 278f7cab0f9SKonstantin Porotchkin bank-name = "armada-3700-sb"; 279f7cab0f9SKonstantin Porotchkin reg = <0x18830 0x4>; 280f7cab0f9SKonstantin Porotchkin pin-count = <30>; 281f7cab0f9SKonstantin Porotchkin }; 282f7cab0f9SKonstantin Porotchkin 28356d53956SStefan Roese comphy: comphy@18300 { 28456d53956SStefan Roese compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700"; 28556d53956SStefan Roese reg = <0x18300 0x28>, 28656d53956SStefan Roese <0x1f300 0x3d000>; 28756d53956SStefan Roese mux-bitcount = <1>; 28856d53956SStefan Roese max-lanes = <2>; 28956d53956SStefan Roese }; 290850db82fSStefan Roese }; 291850db82fSStefan Roese }; 292850db82fSStefan Roese}; 293