1/* 2 * Device Tree Include file for Marvell Armada 375 family SoC 3 * 4 * Copyright (C) 2014 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * 9 * This file is dual-licensed: you can use it either under the terms 10 * of the GPL or the X11 license, at your option. Note that this dual 11 * licensing only applies to this file, and not this project as a 12 * whole. 13 * 14 * a) This file is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of the 17 * License, or (at your option) any later version. 18 * 19 * This file is distributed in the hope that it will be useful 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * Or, alternatively 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include "skeleton.dtsi" 49#include <dt-bindings/interrupt-controller/arm-gic.h> 50#include <dt-bindings/interrupt-controller/irq.h> 51#include <dt-bindings/phy/phy.h> 52 53#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 54 55/ { 56 model = "Marvell Armada 375 family SoC"; 57 compatible = "marvell,armada375"; 58 59 aliases { 60 gpio0 = &gpio0; 61 gpio1 = &gpio1; 62 gpio2 = &gpio2; 63 serial0 = &uart0; 64 serial1 = &uart1; 65 }; 66 67 clocks { 68 /* 2 GHz fixed main PLL */ 69 mainpll: mainpll { 70 compatible = "fixed-clock"; 71 #clock-cells = <0>; 72 clock-frequency = <1000000000>; 73 }; 74 /* 25 MHz reference crystal */ 75 refclk: oscillator { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <25000000>; 79 }; 80 }; 81 82 cpus { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 enable-method = "marvell,armada-375-smp"; 86 87 cpu@0 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a9"; 90 reg = <0>; 91 }; 92 cpu@1 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a9"; 95 reg = <1>; 96 }; 97 }; 98 99 pmu { 100 compatible = "arm,cortex-a9-pmu"; 101 interrupts-extended = <&mpic 3>; 102 }; 103 104 soc { 105 compatible = "marvell,armada375-mbus", "simple-bus"; 106 u-boot,dm-pre-reloc; 107 #address-cells = <2>; 108 #size-cells = <1>; 109 controller = <&mbusc>; 110 interrupt-parent = <&gic>; 111 pcie-mem-aperture = <0xe0000000 0x8000000>; 112 pcie-io-aperture = <0xe8000000 0x100000>; 113 114 bootrom { 115 compatible = "marvell,bootrom"; 116 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>; 117 }; 118 119 devbus-bootcs { 120 compatible = "marvell,mvebu-devbus"; 121 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 122 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 clocks = <&coreclk 0>; 126 status = "disabled"; 127 }; 128 129 devbus-cs0 { 130 compatible = "marvell,mvebu-devbus"; 131 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 132 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 clocks = <&coreclk 0>; 136 status = "disabled"; 137 }; 138 139 devbus-cs1 { 140 compatible = "marvell,mvebu-devbus"; 141 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 142 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 clocks = <&coreclk 0>; 146 status = "disabled"; 147 }; 148 149 devbus-cs2 { 150 compatible = "marvell,mvebu-devbus"; 151 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 152 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 clocks = <&coreclk 0>; 156 status = "disabled"; 157 }; 158 159 devbus-cs3 { 160 compatible = "marvell,mvebu-devbus"; 161 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 162 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 clocks = <&coreclk 0>; 166 status = "disabled"; 167 }; 168 169 internal-regs { 170 compatible = "simple-bus"; 171 u-boot,dm-pre-reloc; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 175 176 L2: cache-controller@8000 { 177 compatible = "arm,pl310-cache"; 178 reg = <0x8000 0x1000>; 179 cache-unified; 180 cache-level = <2>; 181 arm,double-linefill-incr = <1>; 182 arm,double-linefill-wrap = <0>; 183 arm,double-linefill = <1>; 184 prefetch-data = <1>; 185 }; 186 187 scu@c000 { 188 compatible = "arm,cortex-a9-scu"; 189 reg = <0xc000 0x58>; 190 }; 191 192 timer@c600 { 193 compatible = "arm,cortex-a9-twd-timer"; 194 reg = <0xc600 0x20>; 195 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 196 clocks = <&coreclk 2>; 197 }; 198 199 gic: interrupt-controller@d000 { 200 compatible = "arm,cortex-a9-gic"; 201 #interrupt-cells = <3>; 202 #size-cells = <0>; 203 interrupt-controller; 204 reg = <0xd000 0x1000>, 205 <0xc100 0x100>; 206 }; 207 208 mdio { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 compatible = "marvell,orion-mdio"; 212 reg = <0xc0054 0x4>; 213 clocks = <&gateclk 19>; 214 }; 215 216 /* Network controller */ 217 ethernet@f0000 { 218 compatible = "marvell,armada-375-pp2"; 219 reg = <0xf0000 0xa000>, /* Packet Processor regs */ 220 <0xc0000 0x3060>, /* LMS regs */ 221 <0xc4000 0x100>, /* eth0 regs */ 222 <0xc5000 0x100>; /* eth1 regs */ 223 clocks = <&gateclk 3>, <&gateclk 19>; 224 clock-names = "pp_clk", "gop_clk"; 225 status = "disabled"; 226 227 eth0: eth0@c4000 { 228 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 229 port-id = <0>; 230 status = "disabled"; 231 }; 232 233 eth1: eth1@c5000 { 234 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 235 port-id = <1>; 236 status = "disabled"; 237 }; 238 }; 239 240 rtc@10300 { 241 compatible = "marvell,orion-rtc"; 242 reg = <0x10300 0x20>; 243 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 244 }; 245 246 spi0: spi@10600 { 247 compatible = "marvell,armada-375-spi", 248 "marvell,orion-spi"; 249 reg = <0x10600 0x50>; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 cell-index = <0>; 253 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&coreclk 0>; 255 status = "disabled"; 256 }; 257 258 spi1: spi@10680 { 259 compatible = "marvell,armada-375-spi", 260 "marvell,orion-spi"; 261 reg = <0x10680 0x50>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 cell-index = <1>; 265 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&coreclk 0>; 267 status = "disabled"; 268 }; 269 270 i2c0: i2c@11000 { 271 compatible = "marvell,mv64xxx-i2c"; 272 reg = <0x11000 0x20>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 276 timeout-ms = <1000>; 277 clocks = <&coreclk 0>; 278 status = "disabled"; 279 }; 280 281 i2c1: i2c@11100 { 282 compatible = "marvell,mv64xxx-i2c"; 283 reg = <0x11100 0x20>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 287 timeout-ms = <1000>; 288 clocks = <&coreclk 0>; 289 status = "disabled"; 290 }; 291 292 uart0: serial@12000 { 293 compatible = "snps,dw-apb-uart"; 294 reg = <0x12000 0x100>; 295 reg-shift = <2>; 296 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 297 reg-io-width = <1>; 298 clocks = <&coreclk 0>; 299 status = "disabled"; 300 }; 301 302 uart1: serial@12100 { 303 compatible = "snps,dw-apb-uart"; 304 reg = <0x12100 0x100>; 305 reg-shift = <2>; 306 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 307 reg-io-width = <1>; 308 clocks = <&coreclk 0>; 309 status = "disabled"; 310 }; 311 312 pinctrl { 313 compatible = "marvell,mv88f6720-pinctrl"; 314 reg = <0x18000 0x24>; 315 316 i2c0_pins: i2c0-pins { 317 marvell,pins = "mpp14", "mpp15"; 318 marvell,function = "i2c0"; 319 }; 320 321 i2c1_pins: i2c1-pins { 322 marvell,pins = "mpp61", "mpp62"; 323 marvell,function = "i2c1"; 324 }; 325 326 nand_pins: nand-pins { 327 marvell,pins = "mpp0", "mpp1", "mpp2", 328 "mpp3", "mpp4", "mpp5", 329 "mpp6", "mpp7", "mpp8", 330 "mpp9", "mpp10", "mpp11", 331 "mpp12", "mpp13"; 332 marvell,function = "nand"; 333 }; 334 335 sdio_pins: sdio-pins { 336 marvell,pins = "mpp24", "mpp25", "mpp26", 337 "mpp27", "mpp28", "mpp29"; 338 marvell,function = "sd"; 339 }; 340 341 spi0_pins: spi0-pins { 342 marvell,pins = "mpp0", "mpp1", "mpp4", 343 "mpp5", "mpp8", "mpp9"; 344 marvell,function = "spi0"; 345 }; 346 }; 347 348 gpio0: gpio@18100 { 349 compatible = "marvell,orion-gpio"; 350 reg = <0x18100 0x40>; 351 ngpios = <32>; 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 360 }; 361 362 gpio1: gpio@18140 { 363 compatible = "marvell,orion-gpio"; 364 reg = <0x18140 0x40>; 365 ngpios = <32>; 366 gpio-controller; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 374 }; 375 376 gpio2: gpio@18180 { 377 compatible = "marvell,orion-gpio"; 378 reg = <0x18180 0x40>; 379 ngpios = <3>; 380 gpio-controller; 381 #gpio-cells = <2>; 382 interrupt-controller; 383 #interrupt-cells = <2>; 384 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 385 }; 386 387 system-controller@18200 { 388 compatible = "marvell,armada-375-system-controller"; 389 reg = <0x18200 0x100>; 390 }; 391 392 gateclk: clock-gating-control@18220 { 393 compatible = "marvell,armada-375-gating-clock"; 394 reg = <0x18220 0x4>; 395 clocks = <&coreclk 0>; 396 #clock-cells = <1>; 397 }; 398 399 usbcluster: usb-cluster@18400 { 400 compatible = "marvell,armada-375-usb-cluster"; 401 reg = <0x18400 0x4>; 402 #phy-cells = <1>; 403 }; 404 405 mbusc: mbus-controller@20000 { 406 compatible = "marvell,mbus-controller"; 407 reg = <0x20000 0x100>, <0x20180 0x20>; 408 }; 409 410 mpic: interrupt-controller@20a00 { 411 compatible = "marvell,mpic"; 412 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 413 #interrupt-cells = <1>; 414 #size-cells = <1>; 415 interrupt-controller; 416 msi-controller; 417 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 418 }; 419 420 timer@20300 { 421 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer"; 422 reg = <0x20300 0x30>, <0x21040 0x30>; 423 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 424 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 425 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 426 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 427 <&mpic 5>, 428 <&mpic 6>; 429 clocks = <&coreclk 0>, <&refclk>; 430 clock-names = "nbclk", "fixed"; 431 }; 432 433 watchdog@20300 { 434 compatible = "marvell,armada-375-wdt"; 435 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; 436 clocks = <&coreclk 0>, <&refclk>; 437 clock-names = "nbclk", "fixed"; 438 }; 439 440 cpurst@20800 { 441 compatible = "marvell,armada-370-cpu-reset"; 442 reg = <0x20800 0x10>; 443 }; 444 445 coherency-fabric@21010 { 446 compatible = "marvell,armada-375-coherency-fabric"; 447 reg = <0x21010 0x1c>; 448 }; 449 450 usb@50000 { 451 compatible = "marvell,orion-ehci"; 452 reg = <0x50000 0x500>; 453 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&gateclk 18>; 455 phys = <&usbcluster PHY_TYPE_USB2>; 456 phy-names = "usb"; 457 status = "disabled"; 458 }; 459 460 usb@54000 { 461 compatible = "marvell,orion-ehci"; 462 reg = <0x54000 0x500>; 463 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&gateclk 26>; 465 status = "disabled"; 466 }; 467 468 usb3@58000 { 469 compatible = "marvell,armada-375-xhci"; 470 reg = <0x58000 0x20000>,<0x5b880 0x80>; 471 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&gateclk 16>; 473 phys = <&usbcluster PHY_TYPE_USB3>; 474 phy-names = "usb"; 475 status = "disabled"; 476 }; 477 478 xor@60800 { 479 compatible = "marvell,orion-xor"; 480 reg = <0x60800 0x100 481 0x60A00 0x100>; 482 clocks = <&gateclk 22>; 483 status = "okay"; 484 485 xor00 { 486 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 487 dmacap,memcpy; 488 dmacap,xor; 489 }; 490 xor01 { 491 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 492 dmacap,memcpy; 493 dmacap,xor; 494 dmacap,memset; 495 }; 496 }; 497 498 xor@60900 { 499 compatible = "marvell,orion-xor"; 500 reg = <0x60900 0x100 501 0x60b00 0x100>; 502 clocks = <&gateclk 23>; 503 status = "okay"; 504 505 xor10 { 506 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 507 dmacap,memcpy; 508 dmacap,xor; 509 }; 510 xor11 { 511 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 512 dmacap,memcpy; 513 dmacap,xor; 514 dmacap,memset; 515 }; 516 }; 517 518 crypto@90000 { 519 compatible = "marvell,armada-375-crypto"; 520 reg = <0x90000 0x10000>; 521 reg-names = "regs"; 522 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&gateclk 30>, <&gateclk 31>, 525 <&gateclk 28>, <&gateclk 29>; 526 clock-names = "cesa0", "cesa1", 527 "cesaz0", "cesaz1"; 528 marvell,crypto-srams = <&crypto_sram0>, 529 <&crypto_sram1>; 530 marvell,crypto-sram-size = <0x800>; 531 }; 532 533 sata@a0000 { 534 compatible = "marvell,orion-sata"; 535 reg = <0xa0000 0x5000>; 536 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&gateclk 14>, <&gateclk 20>; 538 clock-names = "0", "1"; 539 status = "disabled"; 540 }; 541 542 nand@d0000 { 543 compatible = "marvell,armada370-nand"; 544 reg = <0xd0000 0x54>; 545 #address-cells = <1>; 546 #size-cells = <1>; 547 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&gateclk 11>; 549 status = "disabled"; 550 }; 551 552 mvsdio@d4000 { 553 compatible = "marvell,orion-sdio"; 554 reg = <0xd4000 0x200>; 555 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&gateclk 17>; 557 bus-width = <4>; 558 cap-sdio-irq; 559 cap-sd-highspeed; 560 cap-mmc-highspeed; 561 status = "disabled"; 562 }; 563 564 thermal@e8078 { 565 compatible = "marvell,armada375-thermal"; 566 reg = <0xe8078 0x4>, <0xe807c 0x8>; 567 status = "okay"; 568 }; 569 570 coreclk: mvebu-sar@e8204 { 571 compatible = "marvell,armada-375-core-clock"; 572 reg = <0xe8204 0x04>; 573 #clock-cells = <1>; 574 }; 575 576 coredivclk: corediv-clock@e8250 { 577 compatible = "marvell,armada-375-corediv-clock"; 578 reg = <0xe8250 0xc>; 579 #clock-cells = <1>; 580 clocks = <&mainpll>; 581 clock-output-names = "nand"; 582 }; 583 }; 584 585 pcie-controller { 586 compatible = "marvell,armada-370-pcie"; 587 status = "disabled"; 588 device_type = "pci"; 589 590 #address-cells = <3>; 591 #size-cells = <2>; 592 593 msi-parent = <&mpic>; 594 bus-range = <0x00 0xff>; 595 596 ranges = 597 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 598 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 599 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */ 600 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */ 601 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */ 602 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>; 603 604 pcie@1,0 { 605 device_type = "pci"; 606 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; 607 reg = <0x0800 0 0 0 0>; 608 #address-cells = <3>; 609 #size-cells = <2>; 610 #interrupt-cells = <1>; 611 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 612 0x81000000 0 0 0x81000000 0x1 0 1 0>; 613 interrupt-map-mask = <0 0 0 0>; 614 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 615 marvell,pcie-port = <0>; 616 marvell,pcie-lane = <0>; 617 clocks = <&gateclk 5>; 618 status = "disabled"; 619 }; 620 621 pcie@2,0 { 622 device_type = "pci"; 623 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; 624 reg = <0x1000 0 0 0 0>; 625 #address-cells = <3>; 626 #size-cells = <2>; 627 #interrupt-cells = <1>; 628 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 629 0x81000000 0 0 0x81000000 0x2 0 1 0>; 630 interrupt-map-mask = <0 0 0 0>; 631 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 632 marvell,pcie-port = <0>; 633 marvell,pcie-lane = <1>; 634 clocks = <&gateclk 6>; 635 status = "disabled"; 636 }; 637 638 }; 639 640 crypto_sram0: sa-sram0 { 641 compatible = "mmio-sram"; 642 reg = <MBUS_ID(0x09, 0x09) 0 0x800>; 643 clocks = <&gateclk 30>; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>; 647 }; 648 649 crypto_sram1: sa-sram1 { 650 compatible = "mmio-sram"; 651 reg = <MBUS_ID(0x09, 0x05) 0 0x800>; 652 clocks = <&gateclk 31>; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>; 656 }; 657 }; 658}; 659