1/* 2 * Device Tree Include file for Marvell Armada 370 and Armada XP SoC 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Lior Amsalem <alior@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 9 * Ben Dooks <ben.dooks@codethink.co.uk> 10 * 11 * This file is dual-licensed: you can use it either under the terms 12 * of the GPL or the X11 license, at your option. Note that this dual 13 * licensing only applies to this file, and not this project as a 14 * whole. 15 * 16 * a) This file is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of the 19 * License, or (at your option) any later version. 20 * 21 * This file is distributed in the hope that it will be useful 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * Or, alternatively 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 * 49 * This file contains the definitions that are common to the Armada 50 * 370 and Armada XP SoC. 51 */ 52 53/include/ "skeleton64.dtsi" 54 55#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 56 57/ { 58 model = "Marvell Armada 370 and XP SoC"; 59 compatible = "marvell,armada-370-xp"; 60 61 aliases { 62 serial0 = &uart0; 63 serial1 = &uart1; 64 }; 65 66 cpus { 67 #address-cells = <1>; 68 #size-cells = <0>; 69 cpu@0 { 70 compatible = "marvell,sheeva-v7"; 71 device_type = "cpu"; 72 reg = <0>; 73 }; 74 }; 75 76 pmu { 77 compatible = "arm,cortex-a9-pmu"; 78 interrupts-extended = <&mpic 3>; 79 }; 80 81 soc { 82 #address-cells = <2>; 83 #size-cells = <1>; 84 controller = <&mbusc>; 85 interrupt-parent = <&mpic>; 86 pcie-mem-aperture = <0xf8000000 0x7e00000>; 87 pcie-io-aperture = <0xffe00000 0x100000>; 88 89 devbus-bootcs { 90 compatible = "marvell,mvebu-devbus"; 91 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 92 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 clocks = <&coreclk 0>; 96 status = "disabled"; 97 }; 98 99 devbus-cs0 { 100 compatible = "marvell,mvebu-devbus"; 101 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 102 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 clocks = <&coreclk 0>; 106 status = "disabled"; 107 }; 108 109 devbus-cs1 { 110 compatible = "marvell,mvebu-devbus"; 111 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 112 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 113 #address-cells = <1>; 114 #size-cells = <1>; 115 clocks = <&coreclk 0>; 116 status = "disabled"; 117 }; 118 119 devbus-cs2 { 120 compatible = "marvell,mvebu-devbus"; 121 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 122 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 123 #address-cells = <1>; 124 #size-cells = <1>; 125 clocks = <&coreclk 0>; 126 status = "disabled"; 127 }; 128 129 devbus-cs3 { 130 compatible = "marvell,mvebu-devbus"; 131 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 132 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 clocks = <&coreclk 0>; 136 status = "disabled"; 137 }; 138 139 internal-regs { 140 compatible = "simple-bus"; 141 #address-cells = <1>; 142 #size-cells = <1>; 143 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 144 145 rtc@10300 { 146 compatible = "marvell,orion-rtc"; 147 reg = <0x10300 0x20>; 148 interrupts = <50>; 149 }; 150 151 spi0: spi@10600 { 152 reg = <0x10600 0x28>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 cell-index = <0>; 156 interrupts = <30>; 157 clocks = <&coreclk 0>; 158 status = "disabled"; 159 }; 160 161 spi1: spi@10680 { 162 reg = <0x10680 0x28>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 cell-index = <1>; 166 interrupts = <92>; 167 clocks = <&coreclk 0>; 168 status = "disabled"; 169 }; 170 171 i2c0: i2c@11000 { 172 compatible = "marvell,mv64xxx-i2c"; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 interrupts = <31>; 176 timeout-ms = <1000>; 177 clocks = <&coreclk 0>; 178 status = "disabled"; 179 }; 180 181 i2c1: i2c@11100 { 182 compatible = "marvell,mv64xxx-i2c"; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 interrupts = <32>; 186 timeout-ms = <1000>; 187 clocks = <&coreclk 0>; 188 status = "disabled"; 189 }; 190 191 uart0: serial@12000 { 192 compatible = "snps,dw-apb-uart"; 193 reg = <0x12000 0x100>; 194 reg-shift = <2>; 195 interrupts = <41>; 196 reg-io-width = <1>; 197 clocks = <&coreclk 0>; 198 status = "disabled"; 199 }; 200 201 uart1: serial@12100 { 202 compatible = "snps,dw-apb-uart"; 203 reg = <0x12100 0x100>; 204 reg-shift = <2>; 205 interrupts = <42>; 206 reg-io-width = <1>; 207 clocks = <&coreclk 0>; 208 status = "disabled"; 209 }; 210 211 pinctrl: pin-ctrl@18000 { 212 reg = <0x18000 0x38>; 213 }; 214 215 coredivclk: corediv-clock@18740 { 216 compatible = "marvell,armada-370-corediv-clock"; 217 reg = <0x18740 0xc>; 218 #clock-cells = <1>; 219 clocks = <&mainpll>; 220 clock-output-names = "nand"; 221 }; 222 223 mbusc: mbus-controller@20000 { 224 compatible = "marvell,mbus-controller"; 225 reg = <0x20000 0x100>, <0x20180 0x20>, 226 <0x20250 0x8>; 227 }; 228 229 mpic: interrupt-controller@20a00 { 230 compatible = "marvell,mpic"; 231 #interrupt-cells = <1>; 232 #size-cells = <1>; 233 interrupt-controller; 234 msi-controller; 235 }; 236 237 coherency-fabric@20200 { 238 compatible = "marvell,coherency-fabric"; 239 reg = <0x20200 0xb0>, <0x21010 0x1c>; 240 }; 241 242 timer@20300 { 243 reg = <0x20300 0x30>, <0x21040 0x30>; 244 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 245 }; 246 247 watchdog@20300 { 248 reg = <0x20300 0x34>, <0x20704 0x4>; 249 }; 250 251 pmsu@22000 { 252 compatible = "marvell,armada-370-pmsu"; 253 reg = <0x22000 0x1000>; 254 }; 255 256 usb@50000 { 257 compatible = "marvell,orion-ehci"; 258 reg = <0x50000 0x500>; 259 interrupts = <45>; 260 status = "disabled"; 261 }; 262 263 usb@51000 { 264 compatible = "marvell,orion-ehci"; 265 reg = <0x51000 0x500>; 266 interrupts = <46>; 267 status = "disabled"; 268 }; 269 270 eth0: ethernet@70000 { 271 reg = <0x70000 0x4000>; 272 interrupts = <8>; 273 clocks = <&gateclk 4>; 274 status = "disabled"; 275 }; 276 277 mdio: mdio { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "marvell,orion-mdio"; 281 reg = <0x72004 0x4>; 282 clocks = <&gateclk 4>; 283 }; 284 285 eth1: ethernet@74000 { 286 reg = <0x74000 0x4000>; 287 interrupts = <10>; 288 clocks = <&gateclk 3>; 289 status = "disabled"; 290 }; 291 292 sata@a0000 { 293 compatible = "marvell,armada-370-sata"; 294 reg = <0xa0000 0x5000>; 295 interrupts = <55>; 296 clocks = <&gateclk 15>, <&gateclk 30>; 297 clock-names = "0", "1"; 298 status = "disabled"; 299 }; 300 301 nand@d0000 { 302 compatible = "marvell,armada370-nand"; 303 reg = <0xd0000 0x54>; 304 #address-cells = <1>; 305 #size-cells = <1>; 306 interrupts = <113>; 307 clocks = <&coredivclk 0>; 308 status = "disabled"; 309 }; 310 311 mvsdio@d4000 { 312 compatible = "marvell,orion-sdio"; 313 reg = <0xd4000 0x200>; 314 interrupts = <54>; 315 clocks = <&gateclk 17>; 316 bus-width = <4>; 317 cap-sdio-irq; 318 cap-sd-highspeed; 319 cap-mmc-highspeed; 320 status = "disabled"; 321 }; 322 }; 323 }; 324 325 clocks { 326 /* 2 GHz fixed main PLL */ 327 mainpll: mainpll { 328 compatible = "fixed-clock"; 329 #clock-cells = <0>; 330 clock-frequency = <2000000000>; 331 }; 332 }; 333 }; 334