1/* 2 * Device Tree Source for AM4372 SoC 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14#include "skeleton.dtsi" 15 16/ { 17 compatible = "ti,am4372", "ti,am43"; 18 interrupt-parent = <&wakeupgen>; 19 20 21 aliases { 22 i2c0 = &i2c0; 23 i2c1 = &i2c1; 24 i2c2 = &i2c2; 25 serial0 = &uart0; 26 ethernet0 = &cpsw_emac0; 27 ethernet1 = &cpsw_emac1; 28 spi0 = &qspi; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 cpu: cpu@0 { 35 compatible = "arm,cortex-a9"; 36 device_type = "cpu"; 37 reg = <0>; 38 39 clocks = <&dpll_mpu_ck>; 40 clock-names = "cpu"; 41 42 clock-latency = <300000>; /* From omap-cpufreq driver */ 43 }; 44 }; 45 46 gic: interrupt-controller@48241000 { 47 compatible = "arm,cortex-a9-gic"; 48 interrupt-controller; 49 #interrupt-cells = <3>; 50 reg = <0x48241000 0x1000>, 51 <0x48240100 0x0100>; 52 interrupt-parent = <&gic>; 53 }; 54 55 wakeupgen: interrupt-controller@48281000 { 56 compatible = "ti,omap4-wugen-mpu"; 57 interrupt-controller; 58 #interrupt-cells = <3>; 59 reg = <0x48281000 0x1000>; 60 interrupt-parent = <&gic>; 61 }; 62 63 l2-cache-controller@48242000 { 64 compatible = "arm,pl310-cache"; 65 reg = <0x48242000 0x1000>; 66 cache-unified; 67 cache-level = <2>; 68 }; 69 70 ocp { 71 compatible = "ti,am4372-l3-noc", "simple-bus"; 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges; 75 ti,hwmods = "l3_main"; 76 reg = <0x44000000 0x400000 77 0x44800000 0x400000>; 78 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 80 81 l4_wkup: l4_wkup@44c00000 { 82 compatible = "ti,am4-l4-wkup", "simple-bus"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges = <0 0x44c00000 0x287000>; 86 87 prcm: prcm@1f0000 { 88 compatible = "ti,am4-prcm"; 89 reg = <0x1f0000 0x11000>; 90 91 prcm_clocks: clocks { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 }; 95 96 prcm_clockdomains: clockdomains { 97 }; 98 }; 99 100 scm: scm@210000 { 101 compatible = "ti,am4-scm", "simple-bus"; 102 reg = <0x210000 0x4000>; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 ranges = <0 0x210000 0x4000>; 106 107 am43xx_pinmux: pinmux@800 { 108 compatible = "ti,am437-padconf", 109 "pinctrl-single"; 110 reg = <0x800 0x31c>; 111 #interrupt-cells = <1>; 112 interrupt-controller; 113 pinctrl-single,register-width = <32>; 114 pinctrl-single,function-mask = <0xffffffff>; 115 }; 116 117 scm_conf: scm_conf@0 { 118 compatible = "syscon"; 119 reg = <0x0 0x800>; 120 121 scm_clocks: clocks { 122 #address-cells = <1>; 123 #size-cells = <0>; 124 }; 125 }; 126 127 scm_clockdomains: clockdomains { 128 }; 129 }; 130 }; 131 132 emif: emif@4c000000 { 133 compatible = "ti,emif-am4372"; 134 reg = <0x4c000000 0x1000000>; 135 ti,hwmods = "emif"; 136 }; 137 138 edma: edma@49000000 { 139 compatible = "ti,edma3"; 140 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; 141 reg = <0x49000000 0x10000>, 142 <0x44e10f90 0x10>; 143 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 146 #dma-cells = <1>; 147 }; 148 149 uart0: serial@44e09000 { 150 compatible = "ti,am4372-uart","ti,omap2-uart"; 151 reg = <0x44e09000 0x2000>; 152 reg-shift = <2>; 153 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 154 ti,hwmods = "uart1"; 155 }; 156 157 uart1: serial@48022000 { 158 compatible = "ti,am4372-uart","ti,omap2-uart"; 159 reg = <0x48022000 0x2000>; 160 reg-shift = <2>; 161 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 162 ti,hwmods = "uart2"; 163 status = "disabled"; 164 }; 165 166 uart2: serial@48024000 { 167 compatible = "ti,am4372-uart","ti,omap2-uart"; 168 reg = <0x48024000 0x2000>; 169 reg-shift = <2>; 170 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 171 ti,hwmods = "uart3"; 172 status = "disabled"; 173 }; 174 175 uart3: serial@481a6000 { 176 compatible = "ti,am4372-uart","ti,omap2-uart"; 177 reg = <0x481a6000 0x2000>; 178 reg-shift = <2>; 179 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 180 ti,hwmods = "uart4"; 181 status = "disabled"; 182 }; 183 184 uart4: serial@481a8000 { 185 compatible = "ti,am4372-uart","ti,omap2-uart"; 186 reg = <0x481a8000 0x2000>; 187 reg-shift = <2>; 188 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 189 ti,hwmods = "uart5"; 190 status = "disabled"; 191 }; 192 193 uart5: serial@481aa000 { 194 compatible = "ti,am4372-uart","ti,omap2-uart"; 195 reg = <0x481aa000 0x2000>; 196 reg-shift = <2>; 197 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 198 ti,hwmods = "uart6"; 199 status = "disabled"; 200 }; 201 202 mailbox: mailbox@480C8000 { 203 compatible = "ti,omap4-mailbox"; 204 reg = <0x480C8000 0x200>; 205 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 206 ti,hwmods = "mailbox"; 207 #mbox-cells = <1>; 208 ti,mbox-num-users = <4>; 209 ti,mbox-num-fifos = <8>; 210 mbox_wkupm3: wkup_m3 { 211 ti,mbox-tx = <0 0 0>; 212 ti,mbox-rx = <0 0 3>; 213 }; 214 }; 215 216 timer1: timer@44e31000 { 217 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; 218 reg = <0x44e31000 0x400>; 219 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 220 ti,timer-alwon; 221 ti,hwmods = "timer1"; 222 }; 223 224 timer2: timer@48040000 { 225 compatible = "ti,am4372-timer","ti,am335x-timer"; 226 reg = <0x48040000 0x400>; 227 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 228 ti,hwmods = "timer2"; 229 }; 230 231 timer3: timer@48042000 { 232 compatible = "ti,am4372-timer","ti,am335x-timer"; 233 reg = <0x48042000 0x400>; 234 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 235 ti,hwmods = "timer3"; 236 status = "disabled"; 237 }; 238 239 timer4: timer@48044000 { 240 compatible = "ti,am4372-timer","ti,am335x-timer"; 241 reg = <0x48044000 0x400>; 242 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 243 ti,timer-pwm; 244 ti,hwmods = "timer4"; 245 status = "disabled"; 246 }; 247 248 timer5: timer@48046000 { 249 compatible = "ti,am4372-timer","ti,am335x-timer"; 250 reg = <0x48046000 0x400>; 251 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 252 ti,timer-pwm; 253 ti,hwmods = "timer5"; 254 status = "disabled"; 255 }; 256 257 timer6: timer@48048000 { 258 compatible = "ti,am4372-timer","ti,am335x-timer"; 259 reg = <0x48048000 0x400>; 260 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 261 ti,timer-pwm; 262 ti,hwmods = "timer6"; 263 status = "disabled"; 264 }; 265 266 timer7: timer@4804a000 { 267 compatible = "ti,am4372-timer","ti,am335x-timer"; 268 reg = <0x4804a000 0x400>; 269 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 270 ti,timer-pwm; 271 ti,hwmods = "timer7"; 272 status = "disabled"; 273 }; 274 275 timer8: timer@481c1000 { 276 compatible = "ti,am4372-timer","ti,am335x-timer"; 277 reg = <0x481c1000 0x400>; 278 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 279 ti,hwmods = "timer8"; 280 status = "disabled"; 281 }; 282 283 timer9: timer@4833d000 { 284 compatible = "ti,am4372-timer","ti,am335x-timer"; 285 reg = <0x4833d000 0x400>; 286 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 287 ti,hwmods = "timer9"; 288 status = "disabled"; 289 }; 290 291 timer10: timer@4833f000 { 292 compatible = "ti,am4372-timer","ti,am335x-timer"; 293 reg = <0x4833f000 0x400>; 294 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 295 ti,hwmods = "timer10"; 296 status = "disabled"; 297 }; 298 299 timer11: timer@48341000 { 300 compatible = "ti,am4372-timer","ti,am335x-timer"; 301 reg = <0x48341000 0x400>; 302 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 303 ti,hwmods = "timer11"; 304 status = "disabled"; 305 }; 306 307 counter32k: counter@44e86000 { 308 compatible = "ti,am4372-counter32k","ti,omap-counter32k"; 309 reg = <0x44e86000 0x40>; 310 ti,hwmods = "counter_32k"; 311 }; 312 313 rtc: rtc@44e3e000 { 314 compatible = "ti,am4372-rtc","ti,da830-rtc"; 315 reg = <0x44e3e000 0x1000>; 316 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH 317 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 318 ti,hwmods = "rtc"; 319 status = "disabled"; 320 }; 321 322 wdt: wdt@44e35000 { 323 compatible = "ti,am4372-wdt","ti,omap3-wdt"; 324 reg = <0x44e35000 0x1000>; 325 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 326 ti,hwmods = "wd_timer2"; 327 }; 328 329 gpio0: gpio@44e07000 { 330 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 331 reg = <0x44e07000 0x1000>; 332 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 333 gpio-controller; 334 #gpio-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 ti,hwmods = "gpio1"; 338 status = "disabled"; 339 }; 340 341 gpio1: gpio@4804c000 { 342 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 343 reg = <0x4804c000 0x1000>; 344 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 ti,hwmods = "gpio2"; 350 status = "disabled"; 351 }; 352 353 gpio2: gpio@481ac000 { 354 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 355 reg = <0x481ac000 0x1000>; 356 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 357 gpio-controller; 358 #gpio-cells = <2>; 359 interrupt-controller; 360 #interrupt-cells = <2>; 361 ti,hwmods = "gpio3"; 362 status = "disabled"; 363 }; 364 365 gpio3: gpio@481ae000 { 366 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 367 reg = <0x481ae000 0x1000>; 368 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 369 gpio-controller; 370 #gpio-cells = <2>; 371 interrupt-controller; 372 #interrupt-cells = <2>; 373 ti,hwmods = "gpio4"; 374 status = "disabled"; 375 }; 376 377 gpio4: gpio@48320000 { 378 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 379 reg = <0x48320000 0x1000>; 380 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 ti,hwmods = "gpio5"; 386 status = "disabled"; 387 }; 388 389 gpio5: gpio@48322000 { 390 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 391 reg = <0x48322000 0x1000>; 392 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 393 gpio-controller; 394 #gpio-cells = <2>; 395 interrupt-controller; 396 #interrupt-cells = <2>; 397 ti,hwmods = "gpio6"; 398 status = "disabled"; 399 }; 400 401 hwspinlock: spinlock@480ca000 { 402 compatible = "ti,omap4-hwspinlock"; 403 reg = <0x480ca000 0x1000>; 404 ti,hwmods = "spinlock"; 405 #hwlock-cells = <1>; 406 }; 407 408 i2c0: i2c@44e0b000 { 409 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 410 reg = <0x44e0b000 0x1000>; 411 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 412 ti,hwmods = "i2c1"; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 status = "disabled"; 416 }; 417 418 i2c1: i2c@4802a000 { 419 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 420 reg = <0x4802a000 0x1000>; 421 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 422 ti,hwmods = "i2c2"; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 status = "disabled"; 426 }; 427 428 i2c2: i2c@4819c000 { 429 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 430 reg = <0x4819c000 0x1000>; 431 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 432 ti,hwmods = "i2c3"; 433 #address-cells = <1>; 434 #size-cells = <0>; 435 status = "disabled"; 436 }; 437 438 spi0: spi@48030000 { 439 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 440 reg = <0x48030000 0x400>; 441 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 442 ti,hwmods = "spi0"; 443 #address-cells = <1>; 444 #size-cells = <0>; 445 status = "disabled"; 446 }; 447 448 mmc1: mmc@48060000 { 449 compatible = "ti,omap4-hsmmc"; 450 reg = <0x48060000 0x1000>; 451 ti,hwmods = "mmc1"; 452 ti,dual-volt; 453 ti,needs-special-reset; 454 dmas = <&edma 24 455 &edma 25>; 456 dma-names = "tx", "rx"; 457 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 458 status = "disabled"; 459 }; 460 461 mmc2: mmc@481d8000 { 462 compatible = "ti,omap4-hsmmc"; 463 reg = <0x481d8000 0x1000>; 464 ti,hwmods = "mmc2"; 465 ti,needs-special-reset; 466 dmas = <&edma 2 467 &edma 3>; 468 dma-names = "tx", "rx"; 469 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 470 status = "disabled"; 471 }; 472 473 mmc3: mmc@47810000 { 474 compatible = "ti,omap4-hsmmc"; 475 reg = <0x47810000 0x1000>; 476 ti,hwmods = "mmc3"; 477 ti,needs-special-reset; 478 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 479 status = "disabled"; 480 }; 481 482 spi1: spi@481a0000 { 483 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 484 reg = <0x481a0000 0x400>; 485 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 486 ti,hwmods = "spi1"; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 status = "disabled"; 490 }; 491 492 spi2: spi@481a2000 { 493 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 494 reg = <0x481a2000 0x400>; 495 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 496 ti,hwmods = "spi2"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 status = "disabled"; 500 }; 501 502 spi3: spi@481a4000 { 503 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 504 reg = <0x481a4000 0x400>; 505 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 506 ti,hwmods = "spi3"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 status = "disabled"; 510 }; 511 512 spi4: spi@48345000 { 513 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 514 reg = <0x48345000 0x400>; 515 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 516 ti,hwmods = "spi4"; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 mac: ethernet@4a100000 { 523 compatible = "ti,am4372-cpsw","ti,cpsw"; 524 reg = <0x4a100000 0x800 525 0x4a101200 0x100>; 526 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 527 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 528 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 529 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ti,hwmods = "cpgmac0"; 533 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>; 534 clock-names = "fck", "cpts"; 535 status = "disabled"; 536 cpdma_channels = <8>; 537 ale_entries = <1024>; 538 bd_ram_size = <0x2000>; 539 no_bd_ram = <0>; 540 rx_descs = <64>; 541 mac_control = <0x20>; 542 slaves = <2>; 543 active_slave = <0>; 544 cpts_clock_mult = <0x80000000>; 545 cpts_clock_shift = <29>; 546 syscon = <&scm_conf>; 547 ranges; 548 549 davinci_mdio: mdio@4a101000 { 550 compatible = "ti,am4372-mdio","ti,davinci_mdio"; 551 reg = <0x4a101000 0x100>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 ti,hwmods = "davinci_mdio"; 555 bus_freq = <1000000>; 556 status = "disabled"; 557 }; 558 559 cpsw_emac0: slave@4a100200 { 560 /* Filled in by U-Boot */ 561 mac-address = [ 00 00 00 00 00 00 ]; 562 }; 563 564 cpsw_emac1: slave@4a100300 { 565 /* Filled in by U-Boot */ 566 mac-address = [ 00 00 00 00 00 00 ]; 567 }; 568 569 phy_sel: cpsw-phy-sel@44e10650 { 570 compatible = "ti,am43xx-cpsw-phy-sel"; 571 reg= <0x44e10650 0x4>; 572 reg-names = "gmii-sel"; 573 }; 574 }; 575 576 epwmss0: epwmss@48300000 { 577 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 578 reg = <0x48300000 0x10>; 579 #address-cells = <1>; 580 #size-cells = <1>; 581 ranges; 582 ti,hwmods = "epwmss0"; 583 status = "disabled"; 584 585 ecap0: ecap@48300100 { 586 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 587 #pwm-cells = <3>; 588 reg = <0x48300100 0x80>; 589 ti,hwmods = "ecap0"; 590 status = "disabled"; 591 }; 592 593 ehrpwm0: ehrpwm@48300200 { 594 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 595 #pwm-cells = <3>; 596 reg = <0x48300200 0x80>; 597 ti,hwmods = "ehrpwm0"; 598 status = "disabled"; 599 }; 600 }; 601 602 epwmss1: epwmss@48302000 { 603 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 604 reg = <0x48302000 0x10>; 605 #address-cells = <1>; 606 #size-cells = <1>; 607 ranges; 608 ti,hwmods = "epwmss1"; 609 status = "disabled"; 610 611 ecap1: ecap@48302100 { 612 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 613 #pwm-cells = <3>; 614 reg = <0x48302100 0x80>; 615 ti,hwmods = "ecap1"; 616 status = "disabled"; 617 }; 618 619 ehrpwm1: ehrpwm@48302200 { 620 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 621 #pwm-cells = <3>; 622 reg = <0x48302200 0x80>; 623 ti,hwmods = "ehrpwm1"; 624 status = "disabled"; 625 }; 626 }; 627 628 epwmss2: epwmss@48304000 { 629 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 630 reg = <0x48304000 0x10>; 631 #address-cells = <1>; 632 #size-cells = <1>; 633 ranges; 634 ti,hwmods = "epwmss2"; 635 status = "disabled"; 636 637 ecap2: ecap@48304100 { 638 compatible = "ti,am4372-ecap","ti,am33xx-ecap"; 639 #pwm-cells = <3>; 640 reg = <0x48304100 0x80>; 641 ti,hwmods = "ecap2"; 642 status = "disabled"; 643 }; 644 645 ehrpwm2: ehrpwm@48304200 { 646 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 647 #pwm-cells = <3>; 648 reg = <0x48304200 0x80>; 649 ti,hwmods = "ehrpwm2"; 650 status = "disabled"; 651 }; 652 }; 653 654 epwmss3: epwmss@48306000 { 655 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 656 reg = <0x48306000 0x10>; 657 #address-cells = <1>; 658 #size-cells = <1>; 659 ranges; 660 ti,hwmods = "epwmss3"; 661 status = "disabled"; 662 663 ehrpwm3: ehrpwm@48306200 { 664 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 665 #pwm-cells = <3>; 666 reg = <0x48306200 0x80>; 667 ti,hwmods = "ehrpwm3"; 668 status = "disabled"; 669 }; 670 }; 671 672 epwmss4: epwmss@48308000 { 673 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 674 reg = <0x48308000 0x10>; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 ranges; 678 ti,hwmods = "epwmss4"; 679 status = "disabled"; 680 681 ehrpwm4: ehrpwm@48308200 { 682 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 683 #pwm-cells = <3>; 684 reg = <0x48308200 0x80>; 685 ti,hwmods = "ehrpwm4"; 686 status = "disabled"; 687 }; 688 }; 689 690 epwmss5: epwmss@4830a000 { 691 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 692 reg = <0x4830a000 0x10>; 693 #address-cells = <1>; 694 #size-cells = <1>; 695 ranges; 696 ti,hwmods = "epwmss5"; 697 status = "disabled"; 698 699 ehrpwm5: ehrpwm@4830a200 { 700 compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; 701 #pwm-cells = <3>; 702 reg = <0x4830a200 0x80>; 703 ti,hwmods = "ehrpwm5"; 704 status = "disabled"; 705 }; 706 }; 707 708 tscadc: tscadc@44e0d000 { 709 compatible = "ti,am3359-tscadc"; 710 reg = <0x44e0d000 0x1000>; 711 ti,hwmods = "adc_tsc"; 712 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&adc_tsc_fck>; 714 clock-names = "fck"; 715 status = "disabled"; 716 717 tsc { 718 compatible = "ti,am3359-tsc"; 719 }; 720 721 adc { 722 #io-channel-cells = <1>; 723 compatible = "ti,am3359-adc"; 724 }; 725 726 }; 727 728 sham: sham@53100000 { 729 compatible = "ti,omap5-sham"; 730 ti,hwmods = "sham"; 731 reg = <0x53100000 0x300>; 732 dmas = <&edma 36>; 733 dma-names = "rx"; 734 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 735 }; 736 737 aes: aes@53501000 { 738 compatible = "ti,omap4-aes"; 739 ti,hwmods = "aes"; 740 reg = <0x53501000 0xa0>; 741 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 742 dmas = <&edma 6 743 &edma 5>; 744 dma-names = "tx", "rx"; 745 }; 746 747 des: des@53701000 { 748 compatible = "ti,omap4-des"; 749 ti,hwmods = "des"; 750 reg = <0x53701000 0xa0>; 751 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 752 dmas = <&edma 34 753 &edma 33>; 754 dma-names = "tx", "rx"; 755 }; 756 757 mcasp0: mcasp@48038000 { 758 compatible = "ti,am33xx-mcasp-audio"; 759 ti,hwmods = "mcasp0"; 760 reg = <0x48038000 0x2000>, 761 <0x46000000 0x400000>; 762 reg-names = "mpu", "dat"; 763 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "tx", "rx"; 766 status = "disabled"; 767 dmas = <&edma 8>, 768 <&edma 9>; 769 dma-names = "tx", "rx"; 770 }; 771 772 mcasp1: mcasp@4803C000 { 773 compatible = "ti,am33xx-mcasp-audio"; 774 ti,hwmods = "mcasp1"; 775 reg = <0x4803C000 0x2000>, 776 <0x46400000 0x400000>; 777 reg-names = "mpu", "dat"; 778 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 780 interrupt-names = "tx", "rx"; 781 status = "disabled"; 782 dmas = <&edma 10>, 783 <&edma 11>; 784 dma-names = "tx", "rx"; 785 }; 786 787 elm: elm@48080000 { 788 compatible = "ti,am3352-elm"; 789 reg = <0x48080000 0x2000>; 790 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 791 ti,hwmods = "elm"; 792 clocks = <&l4ls_gclk>; 793 clock-names = "fck"; 794 status = "disabled"; 795 }; 796 797 gpmc: gpmc@50000000 { 798 compatible = "ti,am3352-gpmc"; 799 ti,hwmods = "gpmc"; 800 clocks = <&l3s_gclk>; 801 clock-names = "fck"; 802 reg = <0x50000000 0x2000>; 803 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 804 gpmc,num-cs = <7>; 805 gpmc,num-waitpins = <2>; 806 #address-cells = <2>; 807 #size-cells = <1>; 808 interrupt-controller; 809 #interrupt-cells = <2>; 810 status = "disabled"; 811 }; 812 813 am43xx_control_usb2phy1: control-phy@44e10620 { 814 compatible = "ti,control-phy-usb2-am437"; 815 reg = <0x44e10620 0x4>; 816 reg-names = "power"; 817 }; 818 819 am43xx_control_usb2phy2: control-phy@0x44e10628 { 820 compatible = "ti,control-phy-usb2-am437"; 821 reg = <0x44e10628 0x4>; 822 reg-names = "power"; 823 }; 824 825 ocp2scp0: ocp2scp@483a8000 { 826 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; 827 #address-cells = <1>; 828 #size-cells = <1>; 829 ranges; 830 ti,hwmods = "ocp2scp0"; 831 832 usb2_phy1: phy@483a8000 { 833 compatible = "ti,am437x-usb2"; 834 reg = <0x483a8000 0x8000>; 835 ctrl-module = <&am43xx_control_usb2phy1>; 836 clocks = <&usb_phy0_always_on_clk32k>, 837 <&usb_otg_ss0_refclk960m>; 838 clock-names = "wkupclk", "refclk"; 839 #phy-cells = <0>; 840 status = "disabled"; 841 }; 842 }; 843 844 ocp2scp1: ocp2scp@483e8000 { 845 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; 846 #address-cells = <1>; 847 #size-cells = <1>; 848 ranges; 849 ti,hwmods = "ocp2scp1"; 850 851 usb2_phy2: phy@483e8000 { 852 compatible = "ti,am437x-usb2"; 853 reg = <0x483e8000 0x8000>; 854 ctrl-module = <&am43xx_control_usb2phy2>; 855 clocks = <&usb_phy1_always_on_clk32k>, 856 <&usb_otg_ss1_refclk960m>; 857 clock-names = "wkupclk", "refclk"; 858 #phy-cells = <0>; 859 status = "disabled"; 860 }; 861 }; 862 863 dwc3_1: omap_dwc3@48380000 { 864 compatible = "ti,am437x-dwc3"; 865 ti,hwmods = "usb_otg_ss0"; 866 reg = <0x48380000 0x10000>; 867 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 868 #address-cells = <1>; 869 #size-cells = <1>; 870 utmi-mode = <1>; 871 ranges; 872 873 usb1: usb@48390000 { 874 compatible = "synopsys,dwc3"; 875 reg = <0x48390000 0x10000>; 876 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 877 phys = <&usb2_phy1>; 878 phy-names = "usb2-phy"; 879 maximum-speed = "high-speed"; 880 dr_mode = "otg"; 881 status = "disabled"; 882 snps,dis_u3_susphy_quirk; 883 snps,dis_u2_susphy_quirk; 884 }; 885 }; 886 887 dwc3_2: omap_dwc3@483c0000 { 888 compatible = "ti,am437x-dwc3"; 889 ti,hwmods = "usb_otg_ss1"; 890 reg = <0x483c0000 0x10000>; 891 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 utmi-mode = <1>; 895 ranges; 896 897 usb2: usb@483d0000 { 898 compatible = "synopsys,dwc3"; 899 reg = <0x483d0000 0x10000>; 900 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 901 phys = <&usb2_phy2>; 902 phy-names = "usb2-phy"; 903 maximum-speed = "high-speed"; 904 dr_mode = "otg"; 905 status = "disabled"; 906 snps,dis_u3_susphy_quirk; 907 snps,dis_u2_susphy_quirk; 908 }; 909 }; 910 911 qspi: qspi@47900000 { 912 compatible = "ti,am4372-qspi"; 913 reg = <0x47900000 0x100>, 914 <0x30000000 0x4000000>; 915 reg-names = "qspi_base", "qspi_mmap"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 ti,hwmods = "qspi"; 919 interrupts = <0 138 0x4>; 920 num-cs = <4>; 921 status = "disabled"; 922 }; 923 924 hdq: hdq@48347000 { 925 compatible = "ti,am4372-hdq"; 926 reg = <0x48347000 0x1000>; 927 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&func_12m_clk>; 929 clock-names = "fck"; 930 ti,hwmods = "hdq1w"; 931 status = "disabled"; 932 }; 933 934 dss: dss@4832a000 { 935 compatible = "ti,omap3-dss"; 936 reg = <0x4832a000 0x200>; 937 status = "disabled"; 938 ti,hwmods = "dss_core"; 939 clocks = <&disp_clk>; 940 clock-names = "fck"; 941 #address-cells = <1>; 942 #size-cells = <1>; 943 ranges; 944 945 dispc: dispc@4832a400 { 946 compatible = "ti,omap3-dispc"; 947 reg = <0x4832a400 0x400>; 948 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 949 ti,hwmods = "dss_dispc"; 950 clocks = <&disp_clk>; 951 clock-names = "fck"; 952 }; 953 954 rfbi: rfbi@4832a800 { 955 compatible = "ti,omap3-rfbi"; 956 reg = <0x4832a800 0x100>; 957 ti,hwmods = "dss_rfbi"; 958 clocks = <&disp_clk>; 959 clock-names = "fck"; 960 status = "disabled"; 961 }; 962 }; 963 964 ocmcram: ocmcram@40300000 { 965 compatible = "mmio-sram"; 966 reg = <0x40300000 0x40000>; /* 256k */ 967 }; 968 969 dcan0: can@481cc000 { 970 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 971 ti,hwmods = "d_can0"; 972 clocks = <&dcan0_fck>; 973 clock-names = "fck"; 974 reg = <0x481cc000 0x2000>; 975 syscon-raminit = <&scm_conf 0x644 0>; 976 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 977 status = "disabled"; 978 }; 979 980 dcan1: can@481d0000 { 981 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 982 ti,hwmods = "d_can1"; 983 clocks = <&dcan1_fck>; 984 clock-names = "fck"; 985 reg = <0x481d0000 0x2000>; 986 syscon-raminit = <&scm_conf 0x644 1>; 987 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 988 status = "disabled"; 989 }; 990 991 vpfe0: vpfe@48326000 { 992 compatible = "ti,am437x-vpfe"; 993 reg = <0x48326000 0x2000>; 994 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 995 ti,hwmods = "vpfe0"; 996 status = "disabled"; 997 }; 998 999 vpfe1: vpfe@48328000 { 1000 compatible = "ti,am437x-vpfe"; 1001 reg = <0x48328000 0x2000>; 1002 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1003 ti,hwmods = "vpfe1"; 1004 status = "disabled"; 1005 }; 1006 }; 1007}; 1008 1009/include/ "am43xx-clocks.dtsi" 1010