1/* 2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "am33xx.dtsi" 11#include <dt-bindings/interrupt-controller/irq.h> 12 13/ { 14 model = "TI AM335x EVM"; 15 compatible = "ti,am335x-evm", "ti,am33xx"; 16 17 chosen { 18 stdout-path = &uart0; 19 }; 20 21 cpus { 22 cpu@0 { 23 cpu0-supply = <&vdd1_reg>; 24 }; 25 }; 26 27 memory { 28 device_type = "memory"; 29 reg = <0x80000000 0x10000000>; /* 256 MB */ 30 }; 31 32 vbat: fixedregulator@0 { 33 compatible = "regulator-fixed"; 34 regulator-name = "vbat"; 35 regulator-min-microvolt = <5000000>; 36 regulator-max-microvolt = <5000000>; 37 regulator-boot-on; 38 }; 39 40 lis3_reg: fixedregulator@1 { 41 compatible = "regulator-fixed"; 42 regulator-name = "lis3_reg"; 43 regulator-boot-on; 44 }; 45 46 wlan_en_reg: fixedregulator@2 { 47 compatible = "regulator-fixed"; 48 regulator-name = "wlan-en-regulator"; 49 regulator-min-microvolt = <1800000>; 50 regulator-max-microvolt = <1800000>; 51 52 /* WLAN_EN GPIO for this board - Bank1, pin16 */ 53 gpio = <&gpio1 16 0>; 54 55 /* WLAN card specific delay */ 56 startup-delay-us = <70000>; 57 enable-active-high; 58 }; 59 60 matrix_keypad: matrix_keypad@0 { 61 compatible = "gpio-matrix-keypad"; 62 debounce-delay-ms = <5>; 63 col-scan-delay-us = <2>; 64 65 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ 66 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ 67 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ 68 69 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ 70 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ 71 72 linux,keymap = <0x0000008b /* MENU */ 73 0x0100009e /* BACK */ 74 0x02000069 /* LEFT */ 75 0x0001006a /* RIGHT */ 76 0x0101001c /* ENTER */ 77 0x0201006c>; /* DOWN */ 78 }; 79 80 gpio_keys: volume_keys@0 { 81 compatible = "gpio-keys"; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 autorepeat; 85 86 switch@9 { 87 label = "volume-up"; 88 linux,code = <115>; 89 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 90 gpio-key,wakeup; 91 }; 92 93 switch@10 { 94 label = "volume-down"; 95 linux,code = <114>; 96 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 97 gpio-key,wakeup; 98 }; 99 }; 100 101 backlight { 102 compatible = "pwm-backlight"; 103 pwms = <&ecap0 0 50000 0>; 104 brightness-levels = <0 51 53 56 62 75 101 152 255>; 105 default-brightness-level = <8>; 106 }; 107 108 panel { 109 compatible = "ti,tilcdc,panel"; 110 status = "okay"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&lcd_pins_s0>; 113 panel-info { 114 ac-bias = <255>; 115 ac-bias-intrpt = <0>; 116 dma-burst-sz = <16>; 117 bpp = <32>; 118 fdd = <0x80>; 119 sync-edge = <0>; 120 sync-ctrl = <1>; 121 raster-order = <0>; 122 fifo-th = <0>; 123 }; 124 125 display-timings { 126 800x480p62 { 127 clock-frequency = <30000000>; 128 hactive = <800>; 129 vactive = <480>; 130 hfront-porch = <39>; 131 hback-porch = <39>; 132 hsync-len = <47>; 133 vback-porch = <29>; 134 vfront-porch = <13>; 135 vsync-len = <2>; 136 hsync-active = <1>; 137 vsync-active = <1>; 138 }; 139 }; 140 }; 141 142 sound { 143 compatible = "ti,da830-evm-audio"; 144 ti,model = "AM335x-EVM"; 145 ti,audio-codec = <&tlv320aic3106>; 146 ti,mcasp-controller = <&mcasp1>; 147 ti,codec-clock-rate = <12000000>; 148 ti,audio-routing = 149 "Headphone Jack", "HPLOUT", 150 "Headphone Jack", "HPROUT", 151 "LINE1L", "Line In", 152 "LINE1R", "Line In"; 153 }; 154}; 155 156&am33xx_pinmux { 157 pinctrl-names = "default"; 158 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; 159 160 matrix_keypad_s0: matrix_keypad_s0 { 161 pinctrl-single,pins = < 162 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ 163 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ 164 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ 165 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ 166 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ 167 >; 168 }; 169 170 volume_keys_s0: volume_keys_s0 { 171 pinctrl-single,pins = < 172 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ 173 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ 174 >; 175 }; 176 177 i2c0_pins: pinmux_i2c0_pins { 178 pinctrl-single,pins = < 179 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 180 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 181 >; 182 }; 183 184 i2c1_pins: pinmux_i2c1_pins { 185 pinctrl-single,pins = < 186 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ 187 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 188 >; 189 }; 190 191 uart0_pins: pinmux_uart0_pins { 192 pinctrl-single,pins = < 193 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 194 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 195 >; 196 }; 197 198 uart1_pins: pinmux_uart1_pins { 199 pinctrl-single,pins = < 200 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ 201 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ 202 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ 203 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ 204 >; 205 }; 206 207 clkout2_pin: pinmux_clkout2_pin { 208 pinctrl-single,pins = < 209 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 210 >; 211 }; 212 213 nandflash_pins_s0: nandflash_pins_s0 { 214 pinctrl-single,pins = < 215 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 216 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 217 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 218 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 219 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 220 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 221 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 222 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 223 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 224 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 225 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 226 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 227 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 228 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 229 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 230 >; 231 }; 232 233 ecap0_pins: backlight_pins { 234 pinctrl-single,pins = < 235 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 236 >; 237 }; 238 239 cpsw_default: cpsw_default { 240 pinctrl-single,pins = < 241 /* Slave 1 */ 242 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 243 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 244 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 245 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 246 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 247 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 248 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 249 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 250 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 251 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 252 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 253 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 254 >; 255 }; 256 257 cpsw_sleep: cpsw_sleep { 258 pinctrl-single,pins = < 259 /* Slave 1 reset value */ 260 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 261 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 262 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 263 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 264 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 265 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 266 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 267 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 268 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 269 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 270 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 271 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 272 >; 273 }; 274 275 davinci_mdio_default: davinci_mdio_default { 276 pinctrl-single,pins = < 277 /* MDIO */ 278 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 279 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 280 >; 281 }; 282 283 davinci_mdio_sleep: davinci_mdio_sleep { 284 pinctrl-single,pins = < 285 /* MDIO reset value */ 286 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 287 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 288 >; 289 }; 290 291 mmc1_pins: pinmux_mmc1_pins { 292 pinctrl-single,pins = < 293 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 294 >; 295 }; 296 297 mmc3_pins: pinmux_mmc3_pins { 298 pinctrl-single,pins = < 299 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ 300 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ 301 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ 302 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ 303 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ 304 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ 305 >; 306 }; 307 308 wlan_pins: pinmux_wlan_pins { 309 pinctrl-single,pins = < 310 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ 311 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ 312 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ 313 >; 314 }; 315 316 lcd_pins_s0: lcd_pins_s0 { 317 pinctrl-single,pins = < 318 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ 319 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ 320 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ 321 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ 322 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ 323 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ 324 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ 325 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ 326 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ 327 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ 328 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ 329 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ 330 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ 331 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ 332 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ 333 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ 334 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ 335 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ 336 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ 337 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ 338 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ 339 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ 340 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ 341 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ 342 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ 343 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ 344 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ 345 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ 346 >; 347 }; 348 349 am335x_evm_audio_pins: am335x_evm_audio_pins { 350 pinctrl-single,pins = < 351 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 352 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 353 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 354 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 355 >; 356 }; 357 358 dcan1_pins_default: dcan1_pins_default { 359 pinctrl-single,pins = < 360 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ 361 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ 362 >; 363 }; 364}; 365 366&uart0 { 367 pinctrl-names = "default"; 368 pinctrl-0 = <&uart0_pins>; 369 370 status = "okay"; 371}; 372 373&uart1 { 374 pinctrl-names = "default"; 375 pinctrl-0 = <&uart1_pins>; 376 377 status = "okay"; 378}; 379 380&i2c0 { 381 pinctrl-names = "default"; 382 pinctrl-0 = <&i2c0_pins>; 383 384 status = "okay"; 385 clock-frequency = <400000>; 386 387 tps: tps@2d { 388 reg = <0x2d>; 389 }; 390}; 391 392&usb { 393 status = "okay"; 394}; 395 396&usb_ctrl_mod { 397 status = "okay"; 398}; 399 400&usb0_phy { 401 status = "okay"; 402}; 403 404&usb1_phy { 405 status = "okay"; 406}; 407 408&usb0 { 409 status = "okay"; 410}; 411 412&usb1 { 413 status = "okay"; 414 dr_mode = "host"; 415}; 416 417&cppi41dma { 418 status = "okay"; 419}; 420 421&i2c1 { 422 pinctrl-names = "default"; 423 pinctrl-0 = <&i2c1_pins>; 424 425 status = "okay"; 426 clock-frequency = <100000>; 427 428 lis331dlh: lis331dlh@18 { 429 compatible = "st,lis331dlh", "st,lis3lv02d"; 430 reg = <0x18>; 431 Vdd-supply = <&lis3_reg>; 432 Vdd_IO-supply = <&lis3_reg>; 433 434 st,click-single-x; 435 st,click-single-y; 436 st,click-single-z; 437 st,click-thresh-x = <10>; 438 st,click-thresh-y = <10>; 439 st,click-thresh-z = <10>; 440 st,irq1-click; 441 st,irq2-click; 442 st,wakeup-x-lo; 443 st,wakeup-x-hi; 444 st,wakeup-y-lo; 445 st,wakeup-y-hi; 446 st,wakeup-z-lo; 447 st,wakeup-z-hi; 448 st,min-limit-x = <120>; 449 st,min-limit-y = <120>; 450 st,min-limit-z = <140>; 451 st,max-limit-x = <550>; 452 st,max-limit-y = <550>; 453 st,max-limit-z = <750>; 454 }; 455 456 tsl2550: tsl2550@39 { 457 compatible = "taos,tsl2550"; 458 reg = <0x39>; 459 }; 460 461 tmp275: tmp275@48 { 462 compatible = "ti,tmp275"; 463 reg = <0x48>; 464 }; 465 466 tlv320aic3106: tlv320aic3106@1b { 467 compatible = "ti,tlv320aic3106"; 468 reg = <0x1b>; 469 status = "okay"; 470 471 /* Regulators */ 472 AVDD-supply = <&vaux2_reg>; 473 IOVDD-supply = <&vaux2_reg>; 474 DRVDD-supply = <&vaux2_reg>; 475 DVDD-supply = <&vbat>; 476 }; 477}; 478 479&lcdc { 480 status = "okay"; 481}; 482 483&elm { 484 status = "okay"; 485}; 486 487&epwmss0 { 488 status = "okay"; 489 490 ecap0: ecap@48300100 { 491 status = "okay"; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&ecap0_pins>; 494 }; 495}; 496 497&gpmc { 498 status = "okay"; 499 pinctrl-names = "default"; 500 pinctrl-0 = <&nandflash_pins_s0>; 501 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 502 nand@0,0 { 503 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 504 ti,nand-ecc-opt = "bch8"; 505 ti,elm-id = <&elm>; 506 nand-bus-width = <8>; 507 gpmc,device-width = <1>; 508 gpmc,sync-clk-ps = <0>; 509 gpmc,cs-on-ns = <0>; 510 gpmc,cs-rd-off-ns = <44>; 511 gpmc,cs-wr-off-ns = <44>; 512 gpmc,adv-on-ns = <6>; 513 gpmc,adv-rd-off-ns = <34>; 514 gpmc,adv-wr-off-ns = <44>; 515 gpmc,we-on-ns = <0>; 516 gpmc,we-off-ns = <40>; 517 gpmc,oe-on-ns = <0>; 518 gpmc,oe-off-ns = <54>; 519 gpmc,access-ns = <64>; 520 gpmc,rd-cycle-ns = <82>; 521 gpmc,wr-cycle-ns = <82>; 522 gpmc,wait-on-read = "true"; 523 gpmc,wait-on-write = "true"; 524 gpmc,bus-turnaround-ns = <0>; 525 gpmc,cycle2cycle-delay-ns = <0>; 526 gpmc,clk-activation-ns = <0>; 527 gpmc,wait-monitoring-ns = <0>; 528 gpmc,wr-access-ns = <40>; 529 gpmc,wr-data-mux-bus-ns = <0>; 530 /* MTD partition table */ 531 /* All SPL-* partitions are sized to minimal length 532 * which can be independently programmable. For 533 * NAND flash this is equal to size of erase-block */ 534 #address-cells = <1>; 535 #size-cells = <1>; 536 partition@0 { 537 label = "NAND.SPL"; 538 reg = <0x00000000 0x000020000>; 539 }; 540 partition@1 { 541 label = "NAND.SPL.backup1"; 542 reg = <0x00020000 0x00020000>; 543 }; 544 partition@2 { 545 label = "NAND.SPL.backup2"; 546 reg = <0x00040000 0x00020000>; 547 }; 548 partition@3 { 549 label = "NAND.SPL.backup3"; 550 reg = <0x00060000 0x00020000>; 551 }; 552 partition@4 { 553 label = "NAND.u-boot-spl-os"; 554 reg = <0x00080000 0x00040000>; 555 }; 556 partition@5 { 557 label = "NAND.u-boot"; 558 reg = <0x000C0000 0x00100000>; 559 }; 560 partition@6 { 561 label = "NAND.u-boot-env"; 562 reg = <0x001C0000 0x00020000>; 563 }; 564 partition@7 { 565 label = "NAND.u-boot-env.backup1"; 566 reg = <0x001E0000 0x00020000>; 567 }; 568 partition@8 { 569 label = "NAND.kernel"; 570 reg = <0x00200000 0x00800000>; 571 }; 572 partition@9 { 573 label = "NAND.file-system"; 574 reg = <0x00A00000 0x0F600000>; 575 }; 576 }; 577}; 578 579#include "tps65910.dtsi" 580 581&mcasp1 { 582 pinctrl-names = "default"; 583 pinctrl-0 = <&am335x_evm_audio_pins>; 584 585 status = "okay"; 586 587 op-mode = <0>; /* MCASP_IIS_MODE */ 588 tdm-slots = <2>; 589 /* 4 serializers */ 590 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 591 0 0 1 2 592 >; 593 tx-num-evt = <32>; 594 rx-num-evt = <32>; 595}; 596 597&tps { 598 vcc1-supply = <&vbat>; 599 vcc2-supply = <&vbat>; 600 vcc3-supply = <&vbat>; 601 vcc4-supply = <&vbat>; 602 vcc5-supply = <&vbat>; 603 vcc6-supply = <&vbat>; 604 vcc7-supply = <&vbat>; 605 vccio-supply = <&vbat>; 606 607 regulators { 608 vrtc_reg: regulator@0 { 609 regulator-always-on; 610 }; 611 612 vio_reg: regulator@1 { 613 regulator-always-on; 614 }; 615 616 vdd1_reg: regulator@2 { 617 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 618 regulator-name = "vdd_mpu"; 619 regulator-min-microvolt = <912500>; 620 regulator-max-microvolt = <1312500>; 621 regulator-boot-on; 622 regulator-always-on; 623 }; 624 625 vdd2_reg: regulator@3 { 626 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 627 regulator-name = "vdd_core"; 628 regulator-min-microvolt = <912500>; 629 regulator-max-microvolt = <1150000>; 630 regulator-boot-on; 631 regulator-always-on; 632 }; 633 634 vdd3_reg: regulator@4 { 635 regulator-always-on; 636 }; 637 638 vdig1_reg: regulator@5 { 639 regulator-always-on; 640 }; 641 642 vdig2_reg: regulator@6 { 643 regulator-always-on; 644 }; 645 646 vpll_reg: regulator@7 { 647 regulator-always-on; 648 }; 649 650 vdac_reg: regulator@8 { 651 regulator-always-on; 652 }; 653 654 vaux1_reg: regulator@9 { 655 regulator-always-on; 656 }; 657 658 vaux2_reg: regulator@10 { 659 regulator-always-on; 660 }; 661 662 vaux33_reg: regulator@11 { 663 regulator-always-on; 664 }; 665 666 vmmc_reg: regulator@12 { 667 regulator-min-microvolt = <1800000>; 668 regulator-max-microvolt = <3300000>; 669 regulator-always-on; 670 }; 671 }; 672}; 673 674&mac { 675 pinctrl-names = "default", "sleep"; 676 pinctrl-0 = <&cpsw_default>; 677 pinctrl-1 = <&cpsw_sleep>; 678 status = "okay"; 679}; 680 681&davinci_mdio { 682 pinctrl-names = "default", "sleep"; 683 pinctrl-0 = <&davinci_mdio_default>; 684 pinctrl-1 = <&davinci_mdio_sleep>; 685 status = "okay"; 686}; 687 688&cpsw_emac0 { 689 phy_id = <&davinci_mdio>, <0>; 690 phy-mode = "rgmii-txid"; 691}; 692 693&cpsw_emac1 { 694 phy_id = <&davinci_mdio>, <1>; 695 phy-mode = "rgmii-txid"; 696}; 697 698&tscadc { 699 status = "okay"; 700 tsc { 701 ti,wires = <4>; 702 ti,x-plate-resistance = <200>; 703 ti,coordinate-readouts = <5>; 704 ti,wire-config = <0x00 0x11 0x22 0x33>; 705 ti,charge-delay = <0x400>; 706 }; 707 708 adc { 709 ti,adc-channels = <4 5 6 7>; 710 }; 711}; 712 713&mmc1 { 714 status = "okay"; 715 vmmc-supply = <&vmmc_reg>; 716 bus-width = <4>; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&mmc1_pins>; 719 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 720}; 721 722&mmc3 { 723 /* these are on the crossbar and are outlined in the 724 xbar-event-map element */ 725 dmas = <&edma 12 726 &edma 13>; 727 dma-names = "tx", "rx"; 728 status = "okay"; 729 vmmc-supply = <&wlan_en_reg>; 730 bus-width = <4>; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&mmc3_pins &wlan_pins>; 733 ti,non-removable; 734 ti,needs-special-hs-handling; 735 cap-power-off-card; 736 keep-power-in-suspend; 737 738 #address-cells = <1>; 739 #size-cells = <0>; 740 wlcore: wlcore@0 { 741 compatible = "ti,wl1835"; 742 reg = <2>; 743 interrupt-parent = <&gpio3>; 744 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 745 }; 746}; 747 748&edma { 749 ti,edma-xbar-event-map = /bits/ 16 <1 12 750 2 13>; 751}; 752 753&sham { 754 status = "okay"; 755}; 756 757&aes { 758 status = "okay"; 759}; 760 761&dcan1 { 762 status = "disabled"; /* Enable only if Profile 1 is selected */ 763 pinctrl-names = "default"; 764 pinctrl-0 = <&dcan1_pins_default>; 765}; 766