11480fdf8STom Rini/* 21480fdf8STom Rini * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 31480fdf8STom Rini * 41480fdf8STom Rini * This program is free software; you can redistribute it and/or modify 51480fdf8STom Rini * it under the terms of the GNU General Public License version 2 as 61480fdf8STom Rini * published by the Free Software Foundation. 71480fdf8STom Rini */ 81480fdf8STom Rini/dts-v1/; 91480fdf8STom Rini 101480fdf8STom Rini#include "am33xx.dtsi" 111480fdf8STom Rini#include <dt-bindings/interrupt-controller/irq.h> 121480fdf8STom Rini 131480fdf8STom Rini/ { 141480fdf8STom Rini model = "TI AM335x EVM"; 151480fdf8STom Rini compatible = "ti,am335x-evm", "ti,am33xx"; 161480fdf8STom Rini 171480fdf8STom Rini chosen { 181480fdf8STom Rini stdout-path = &uart0; 19d3e25aedSMugunthan V N tick-timer = &timer2; 201480fdf8STom Rini }; 211480fdf8STom Rini 221480fdf8STom Rini cpus { 231480fdf8STom Rini cpu@0 { 241480fdf8STom Rini cpu0-supply = <&vdd1_reg>; 251480fdf8STom Rini }; 261480fdf8STom Rini }; 271480fdf8STom Rini 281480fdf8STom Rini memory { 291480fdf8STom Rini device_type = "memory"; 301480fdf8STom Rini reg = <0x80000000 0x10000000>; /* 256 MB */ 311480fdf8STom Rini }; 321480fdf8STom Rini 331480fdf8STom Rini vbat: fixedregulator@0 { 341480fdf8STom Rini compatible = "regulator-fixed"; 351480fdf8STom Rini regulator-name = "vbat"; 361480fdf8STom Rini regulator-min-microvolt = <5000000>; 371480fdf8STom Rini regulator-max-microvolt = <5000000>; 381480fdf8STom Rini regulator-boot-on; 391480fdf8STom Rini }; 401480fdf8STom Rini 411480fdf8STom Rini lis3_reg: fixedregulator@1 { 421480fdf8STom Rini compatible = "regulator-fixed"; 431480fdf8STom Rini regulator-name = "lis3_reg"; 441480fdf8STom Rini regulator-boot-on; 451480fdf8STom Rini }; 461480fdf8STom Rini 471480fdf8STom Rini wlan_en_reg: fixedregulator@2 { 481480fdf8STom Rini compatible = "regulator-fixed"; 491480fdf8STom Rini regulator-name = "wlan-en-regulator"; 501480fdf8STom Rini regulator-min-microvolt = <1800000>; 511480fdf8STom Rini regulator-max-microvolt = <1800000>; 521480fdf8STom Rini 531480fdf8STom Rini /* WLAN_EN GPIO for this board - Bank1, pin16 */ 541480fdf8STom Rini gpio = <&gpio1 16 0>; 551480fdf8STom Rini 561480fdf8STom Rini /* WLAN card specific delay */ 571480fdf8STom Rini startup-delay-us = <70000>; 581480fdf8STom Rini enable-active-high; 591480fdf8STom Rini }; 601480fdf8STom Rini 611480fdf8STom Rini matrix_keypad: matrix_keypad@0 { 621480fdf8STom Rini compatible = "gpio-matrix-keypad"; 631480fdf8STom Rini debounce-delay-ms = <5>; 641480fdf8STom Rini col-scan-delay-us = <2>; 651480fdf8STom Rini 661480fdf8STom Rini row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ 671480fdf8STom Rini &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ 681480fdf8STom Rini &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ 691480fdf8STom Rini 701480fdf8STom Rini col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ 711480fdf8STom Rini &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ 721480fdf8STom Rini 731480fdf8STom Rini linux,keymap = <0x0000008b /* MENU */ 741480fdf8STom Rini 0x0100009e /* BACK */ 751480fdf8STom Rini 0x02000069 /* LEFT */ 761480fdf8STom Rini 0x0001006a /* RIGHT */ 771480fdf8STom Rini 0x0101001c /* ENTER */ 781480fdf8STom Rini 0x0201006c>; /* DOWN */ 791480fdf8STom Rini }; 801480fdf8STom Rini 811480fdf8STom Rini gpio_keys: volume_keys@0 { 821480fdf8STom Rini compatible = "gpio-keys"; 831480fdf8STom Rini autorepeat; 841480fdf8STom Rini 851480fdf8STom Rini switch@9 { 861480fdf8STom Rini label = "volume-up"; 871480fdf8STom Rini linux,code = <115>; 881480fdf8STom Rini gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 891480fdf8STom Rini gpio-key,wakeup; 901480fdf8STom Rini }; 911480fdf8STom Rini 921480fdf8STom Rini switch@10 { 931480fdf8STom Rini label = "volume-down"; 941480fdf8STom Rini linux,code = <114>; 951480fdf8STom Rini gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 961480fdf8STom Rini gpio-key,wakeup; 971480fdf8STom Rini }; 981480fdf8STom Rini }; 991480fdf8STom Rini 1001480fdf8STom Rini backlight { 1011480fdf8STom Rini compatible = "pwm-backlight"; 1021480fdf8STom Rini pwms = <&ecap0 0 50000 0>; 1031480fdf8STom Rini brightness-levels = <0 51 53 56 62 75 101 152 255>; 1041480fdf8STom Rini default-brightness-level = <8>; 1051480fdf8STom Rini }; 1061480fdf8STom Rini 1071480fdf8STom Rini panel { 1081480fdf8STom Rini compatible = "ti,tilcdc,panel"; 1091480fdf8STom Rini status = "okay"; 1101480fdf8STom Rini pinctrl-names = "default"; 1111480fdf8STom Rini pinctrl-0 = <&lcd_pins_s0>; 1121480fdf8STom Rini panel-info { 1131480fdf8STom Rini ac-bias = <255>; 1141480fdf8STom Rini ac-bias-intrpt = <0>; 1151480fdf8STom Rini dma-burst-sz = <16>; 1161480fdf8STom Rini bpp = <32>; 1171480fdf8STom Rini fdd = <0x80>; 1181480fdf8STom Rini sync-edge = <0>; 1191480fdf8STom Rini sync-ctrl = <1>; 1201480fdf8STom Rini raster-order = <0>; 1211480fdf8STom Rini fifo-th = <0>; 1221480fdf8STom Rini }; 1231480fdf8STom Rini 1241480fdf8STom Rini display-timings { 1251480fdf8STom Rini 800x480p62 { 1261480fdf8STom Rini clock-frequency = <30000000>; 1271480fdf8STom Rini hactive = <800>; 1281480fdf8STom Rini vactive = <480>; 1291480fdf8STom Rini hfront-porch = <39>; 1301480fdf8STom Rini hback-porch = <39>; 1311480fdf8STom Rini hsync-len = <47>; 1321480fdf8STom Rini vback-porch = <29>; 1331480fdf8STom Rini vfront-porch = <13>; 1341480fdf8STom Rini vsync-len = <2>; 1351480fdf8STom Rini hsync-active = <1>; 1361480fdf8STom Rini vsync-active = <1>; 1371480fdf8STom Rini }; 1381480fdf8STom Rini }; 1391480fdf8STom Rini }; 1401480fdf8STom Rini 1411480fdf8STom Rini sound { 1421480fdf8STom Rini compatible = "ti,da830-evm-audio"; 1431480fdf8STom Rini ti,model = "AM335x-EVM"; 1441480fdf8STom Rini ti,audio-codec = <&tlv320aic3106>; 1451480fdf8STom Rini ti,mcasp-controller = <&mcasp1>; 1461480fdf8STom Rini ti,codec-clock-rate = <12000000>; 1471480fdf8STom Rini ti,audio-routing = 1481480fdf8STom Rini "Headphone Jack", "HPLOUT", 1491480fdf8STom Rini "Headphone Jack", "HPROUT", 1501480fdf8STom Rini "LINE1L", "Line In", 1511480fdf8STom Rini "LINE1R", "Line In"; 1521480fdf8STom Rini }; 1531480fdf8STom Rini}; 1541480fdf8STom Rini 1551480fdf8STom Rini&am33xx_pinmux { 1561480fdf8STom Rini pinctrl-names = "default"; 1571480fdf8STom Rini pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; 1581480fdf8STom Rini 1591480fdf8STom Rini matrix_keypad_s0: matrix_keypad_s0 { 1601480fdf8STom Rini pinctrl-single,pins = < 1611480fdf8STom Rini 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ 1621480fdf8STom Rini 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ 1631480fdf8STom Rini 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ 1641480fdf8STom Rini 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ 1651480fdf8STom Rini 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ 1661480fdf8STom Rini >; 1671480fdf8STom Rini }; 1681480fdf8STom Rini 1691480fdf8STom Rini volume_keys_s0: volume_keys_s0 { 1701480fdf8STom Rini pinctrl-single,pins = < 1711480fdf8STom Rini 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ 1721480fdf8STom Rini 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ 1731480fdf8STom Rini >; 1741480fdf8STom Rini }; 1751480fdf8STom Rini 1761480fdf8STom Rini i2c0_pins: pinmux_i2c0_pins { 1771480fdf8STom Rini pinctrl-single,pins = < 1781480fdf8STom Rini 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 1791480fdf8STom Rini 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 1801480fdf8STom Rini >; 1811480fdf8STom Rini }; 1821480fdf8STom Rini 1831480fdf8STom Rini i2c1_pins: pinmux_i2c1_pins { 1841480fdf8STom Rini pinctrl-single,pins = < 1851480fdf8STom Rini 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ 1861480fdf8STom Rini 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 1871480fdf8STom Rini >; 1881480fdf8STom Rini }; 1891480fdf8STom Rini 1901480fdf8STom Rini uart0_pins: pinmux_uart0_pins { 1911480fdf8STom Rini pinctrl-single,pins = < 1921480fdf8STom Rini 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 1931480fdf8STom Rini 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 1941480fdf8STom Rini >; 1951480fdf8STom Rini }; 1961480fdf8STom Rini 1971480fdf8STom Rini uart1_pins: pinmux_uart1_pins { 1981480fdf8STom Rini pinctrl-single,pins = < 1991480fdf8STom Rini 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */ 2001480fdf8STom Rini 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */ 2011480fdf8STom Rini 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */ 2021480fdf8STom Rini 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */ 2031480fdf8STom Rini >; 2041480fdf8STom Rini }; 2051480fdf8STom Rini 2061480fdf8STom Rini clkout2_pin: pinmux_clkout2_pin { 2071480fdf8STom Rini pinctrl-single,pins = < 2081480fdf8STom Rini 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 2091480fdf8STom Rini >; 2101480fdf8STom Rini }; 2111480fdf8STom Rini 2121480fdf8STom Rini nandflash_pins_s0: nandflash_pins_s0 { 2131480fdf8STom Rini pinctrl-single,pins = < 2141480fdf8STom Rini 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 2151480fdf8STom Rini 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 2161480fdf8STom Rini 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 2171480fdf8STom Rini 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 2181480fdf8STom Rini 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 2191480fdf8STom Rini 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 2201480fdf8STom Rini 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 2211480fdf8STom Rini 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 2221480fdf8STom Rini 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 2231480fdf8STom Rini 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 2241480fdf8STom Rini 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 2251480fdf8STom Rini 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 2261480fdf8STom Rini 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 2271480fdf8STom Rini 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 2281480fdf8STom Rini 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 2291480fdf8STom Rini >; 2301480fdf8STom Rini }; 2311480fdf8STom Rini 2321480fdf8STom Rini ecap0_pins: backlight_pins { 2331480fdf8STom Rini pinctrl-single,pins = < 2341480fdf8STom Rini 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 2351480fdf8STom Rini >; 2361480fdf8STom Rini }; 2371480fdf8STom Rini 2381480fdf8STom Rini cpsw_default: cpsw_default { 2391480fdf8STom Rini pinctrl-single,pins = < 2401480fdf8STom Rini /* Slave 1 */ 2411480fdf8STom Rini 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 2421480fdf8STom Rini 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 2431480fdf8STom Rini 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 2441480fdf8STom Rini 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 2451480fdf8STom Rini 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 2461480fdf8STom Rini 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 2471480fdf8STom Rini 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 2481480fdf8STom Rini 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 2491480fdf8STom Rini 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 2501480fdf8STom Rini 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 2511480fdf8STom Rini 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 2521480fdf8STom Rini 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 2531480fdf8STom Rini >; 2541480fdf8STom Rini }; 2551480fdf8STom Rini 2561480fdf8STom Rini cpsw_sleep: cpsw_sleep { 2571480fdf8STom Rini pinctrl-single,pins = < 2581480fdf8STom Rini /* Slave 1 reset value */ 2591480fdf8STom Rini 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2601480fdf8STom Rini 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2611480fdf8STom Rini 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 2621480fdf8STom Rini 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2631480fdf8STom Rini 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2641480fdf8STom Rini 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2651480fdf8STom Rini 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 2661480fdf8STom Rini 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2671480fdf8STom Rini 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2681480fdf8STom Rini 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2691480fdf8STom Rini 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 2701480fdf8STom Rini 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2711480fdf8STom Rini >; 2721480fdf8STom Rini }; 2731480fdf8STom Rini 2741480fdf8STom Rini davinci_mdio_default: davinci_mdio_default { 2751480fdf8STom Rini pinctrl-single,pins = < 2761480fdf8STom Rini /* MDIO */ 2771480fdf8STom Rini 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 2781480fdf8STom Rini 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 2791480fdf8STom Rini >; 2801480fdf8STom Rini }; 2811480fdf8STom Rini 2821480fdf8STom Rini davinci_mdio_sleep: davinci_mdio_sleep { 2831480fdf8STom Rini pinctrl-single,pins = < 2841480fdf8STom Rini /* MDIO reset value */ 2851480fdf8STom Rini 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 2861480fdf8STom Rini 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 2871480fdf8STom Rini >; 2881480fdf8STom Rini }; 2891480fdf8STom Rini 2901480fdf8STom Rini mmc1_pins: pinmux_mmc1_pins { 2911480fdf8STom Rini pinctrl-single,pins = < 2921480fdf8STom Rini 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 2931480fdf8STom Rini >; 2941480fdf8STom Rini }; 2951480fdf8STom Rini 2961480fdf8STom Rini mmc3_pins: pinmux_mmc3_pins { 2971480fdf8STom Rini pinctrl-single,pins = < 2981480fdf8STom Rini 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ 2991480fdf8STom Rini 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ 3001480fdf8STom Rini 0x4C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ 3011480fdf8STom Rini 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ 3021480fdf8STom Rini 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ 3031480fdf8STom Rini 0x8C (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ 3041480fdf8STom Rini >; 3051480fdf8STom Rini }; 3061480fdf8STom Rini 3071480fdf8STom Rini wlan_pins: pinmux_wlan_pins { 3081480fdf8STom Rini pinctrl-single,pins = < 3091480fdf8STom Rini 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */ 3101480fdf8STom Rini 0x19C (PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ 3111480fdf8STom Rini 0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ 3121480fdf8STom Rini >; 3131480fdf8STom Rini }; 3141480fdf8STom Rini 3151480fdf8STom Rini lcd_pins_s0: lcd_pins_s0 { 3161480fdf8STom Rini pinctrl-single,pins = < 3171480fdf8STom Rini 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ 3181480fdf8STom Rini 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ 3191480fdf8STom Rini 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ 3201480fdf8STom Rini 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ 3211480fdf8STom Rini 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ 3221480fdf8STom Rini 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ 3231480fdf8STom Rini 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ 3241480fdf8STom Rini 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ 3251480fdf8STom Rini 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ 3261480fdf8STom Rini 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ 3271480fdf8STom Rini 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ 3281480fdf8STom Rini 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ 3291480fdf8STom Rini 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ 3301480fdf8STom Rini 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ 3311480fdf8STom Rini 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ 3321480fdf8STom Rini 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ 3331480fdf8STom Rini 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ 3341480fdf8STom Rini 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ 3351480fdf8STom Rini 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ 3361480fdf8STom Rini 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ 3371480fdf8STom Rini 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ 3381480fdf8STom Rini 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ 3391480fdf8STom Rini 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ 3401480fdf8STom Rini 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ 3411480fdf8STom Rini 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ 3421480fdf8STom Rini 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ 3431480fdf8STom Rini 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ 3441480fdf8STom Rini 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ 3451480fdf8STom Rini >; 3461480fdf8STom Rini }; 3471480fdf8STom Rini 3481480fdf8STom Rini am335x_evm_audio_pins: am335x_evm_audio_pins { 3491480fdf8STom Rini pinctrl-single,pins = < 3501480fdf8STom Rini 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 3511480fdf8STom Rini 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 3521480fdf8STom Rini 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 3531480fdf8STom Rini 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 3541480fdf8STom Rini >; 3551480fdf8STom Rini }; 3561480fdf8STom Rini 3571480fdf8STom Rini dcan1_pins_default: dcan1_pins_default { 3581480fdf8STom Rini pinctrl-single,pins = < 3591480fdf8STom Rini 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ 3601480fdf8STom Rini 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ 3611480fdf8STom Rini >; 3621480fdf8STom Rini }; 3631480fdf8STom Rini}; 3641480fdf8STom Rini 3651480fdf8STom Rini&uart0 { 3661480fdf8STom Rini pinctrl-names = "default"; 3671480fdf8STom Rini pinctrl-0 = <&uart0_pins>; 3681480fdf8STom Rini 3691480fdf8STom Rini status = "okay"; 3701480fdf8STom Rini}; 3711480fdf8STom Rini 3721480fdf8STom Rini&uart1 { 3731480fdf8STom Rini pinctrl-names = "default"; 3741480fdf8STom Rini pinctrl-0 = <&uart1_pins>; 3751480fdf8STom Rini 3761480fdf8STom Rini status = "okay"; 3771480fdf8STom Rini}; 3781480fdf8STom Rini 3791480fdf8STom Rini&i2c0 { 3801480fdf8STom Rini pinctrl-names = "default"; 3811480fdf8STom Rini pinctrl-0 = <&i2c0_pins>; 3821480fdf8STom Rini 3831480fdf8STom Rini status = "okay"; 3841480fdf8STom Rini clock-frequency = <400000>; 3851480fdf8STom Rini 3861480fdf8STom Rini tps: tps@2d { 3871480fdf8STom Rini reg = <0x2d>; 3881480fdf8STom Rini }; 3891480fdf8STom Rini}; 3901480fdf8STom Rini 3911480fdf8STom Rini&usb { 3921480fdf8STom Rini status = "okay"; 3931480fdf8STom Rini}; 3941480fdf8STom Rini 3951480fdf8STom Rini&usb_ctrl_mod { 3961480fdf8STom Rini status = "okay"; 3971480fdf8STom Rini}; 3981480fdf8STom Rini 3991480fdf8STom Rini&usb0_phy { 4001480fdf8STom Rini status = "okay"; 4011480fdf8STom Rini}; 4021480fdf8STom Rini 4031480fdf8STom Rini&usb1_phy { 4041480fdf8STom Rini status = "okay"; 4051480fdf8STom Rini}; 4061480fdf8STom Rini 4071480fdf8STom Rini&usb0 { 4081480fdf8STom Rini status = "okay"; 4091480fdf8STom Rini}; 4101480fdf8STom Rini 4111480fdf8STom Rini&usb1 { 4121480fdf8STom Rini status = "okay"; 4131480fdf8STom Rini dr_mode = "host"; 4141480fdf8STom Rini}; 4151480fdf8STom Rini 4161480fdf8STom Rini&cppi41dma { 4171480fdf8STom Rini status = "okay"; 4181480fdf8STom Rini}; 4191480fdf8STom Rini 4201480fdf8STom Rini&i2c1 { 4211480fdf8STom Rini pinctrl-names = "default"; 4221480fdf8STom Rini pinctrl-0 = <&i2c1_pins>; 4231480fdf8STom Rini 4241480fdf8STom Rini status = "okay"; 4251480fdf8STom Rini clock-frequency = <100000>; 4261480fdf8STom Rini 4271480fdf8STom Rini lis331dlh: lis331dlh@18 { 4281480fdf8STom Rini compatible = "st,lis331dlh", "st,lis3lv02d"; 4291480fdf8STom Rini reg = <0x18>; 4301480fdf8STom Rini Vdd-supply = <&lis3_reg>; 4311480fdf8STom Rini Vdd_IO-supply = <&lis3_reg>; 4321480fdf8STom Rini 4331480fdf8STom Rini st,click-single-x; 4341480fdf8STom Rini st,click-single-y; 4351480fdf8STom Rini st,click-single-z; 4361480fdf8STom Rini st,click-thresh-x = <10>; 4371480fdf8STom Rini st,click-thresh-y = <10>; 4381480fdf8STom Rini st,click-thresh-z = <10>; 4391480fdf8STom Rini st,irq1-click; 4401480fdf8STom Rini st,irq2-click; 4411480fdf8STom Rini st,wakeup-x-lo; 4421480fdf8STom Rini st,wakeup-x-hi; 4431480fdf8STom Rini st,wakeup-y-lo; 4441480fdf8STom Rini st,wakeup-y-hi; 4451480fdf8STom Rini st,wakeup-z-lo; 4461480fdf8STom Rini st,wakeup-z-hi; 4471480fdf8STom Rini st,min-limit-x = <120>; 4481480fdf8STom Rini st,min-limit-y = <120>; 4491480fdf8STom Rini st,min-limit-z = <140>; 4501480fdf8STom Rini st,max-limit-x = <550>; 4511480fdf8STom Rini st,max-limit-y = <550>; 4521480fdf8STom Rini st,max-limit-z = <750>; 4531480fdf8STom Rini }; 4541480fdf8STom Rini 4551480fdf8STom Rini tsl2550: tsl2550@39 { 4561480fdf8STom Rini compatible = "taos,tsl2550"; 4571480fdf8STom Rini reg = <0x39>; 4581480fdf8STom Rini }; 4591480fdf8STom Rini 4601480fdf8STom Rini tmp275: tmp275@48 { 4611480fdf8STom Rini compatible = "ti,tmp275"; 4621480fdf8STom Rini reg = <0x48>; 4631480fdf8STom Rini }; 4641480fdf8STom Rini 4651480fdf8STom Rini tlv320aic3106: tlv320aic3106@1b { 4661480fdf8STom Rini compatible = "ti,tlv320aic3106"; 4671480fdf8STom Rini reg = <0x1b>; 4681480fdf8STom Rini status = "okay"; 4691480fdf8STom Rini 4701480fdf8STom Rini /* Regulators */ 4711480fdf8STom Rini AVDD-supply = <&vaux2_reg>; 4721480fdf8STom Rini IOVDD-supply = <&vaux2_reg>; 4731480fdf8STom Rini DRVDD-supply = <&vaux2_reg>; 4741480fdf8STom Rini DVDD-supply = <&vbat>; 4751480fdf8STom Rini }; 4761480fdf8STom Rini}; 4771480fdf8STom Rini 4781480fdf8STom Rini&lcdc { 4791480fdf8STom Rini status = "okay"; 4801480fdf8STom Rini}; 4811480fdf8STom Rini 4821480fdf8STom Rini&elm { 4831480fdf8STom Rini status = "okay"; 4841480fdf8STom Rini}; 4851480fdf8STom Rini 4861480fdf8STom Rini&epwmss0 { 4871480fdf8STom Rini status = "okay"; 4881480fdf8STom Rini 4891480fdf8STom Rini ecap0: ecap@48300100 { 4901480fdf8STom Rini status = "okay"; 4911480fdf8STom Rini pinctrl-names = "default"; 4921480fdf8STom Rini pinctrl-0 = <&ecap0_pins>; 4931480fdf8STom Rini }; 4941480fdf8STom Rini}; 4951480fdf8STom Rini 4961480fdf8STom Rini&gpmc { 4971480fdf8STom Rini status = "okay"; 4981480fdf8STom Rini pinctrl-names = "default"; 4991480fdf8STom Rini pinctrl-0 = <&nandflash_pins_s0>; 5001480fdf8STom Rini ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 5011480fdf8STom Rini nand@0,0 { 5021480fdf8STom Rini reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 5031480fdf8STom Rini ti,nand-ecc-opt = "bch8"; 5041480fdf8STom Rini ti,elm-id = <&elm>; 5051480fdf8STom Rini nand-bus-width = <8>; 5061480fdf8STom Rini gpmc,device-width = <1>; 5071480fdf8STom Rini gpmc,sync-clk-ps = <0>; 5081480fdf8STom Rini gpmc,cs-on-ns = <0>; 5091480fdf8STom Rini gpmc,cs-rd-off-ns = <44>; 5101480fdf8STom Rini gpmc,cs-wr-off-ns = <44>; 5111480fdf8STom Rini gpmc,adv-on-ns = <6>; 5121480fdf8STom Rini gpmc,adv-rd-off-ns = <34>; 5131480fdf8STom Rini gpmc,adv-wr-off-ns = <44>; 5141480fdf8STom Rini gpmc,we-on-ns = <0>; 5151480fdf8STom Rini gpmc,we-off-ns = <40>; 5161480fdf8STom Rini gpmc,oe-on-ns = <0>; 5171480fdf8STom Rini gpmc,oe-off-ns = <54>; 5181480fdf8STom Rini gpmc,access-ns = <64>; 5191480fdf8STom Rini gpmc,rd-cycle-ns = <82>; 5201480fdf8STom Rini gpmc,wr-cycle-ns = <82>; 5211480fdf8STom Rini gpmc,wait-on-read = "true"; 5221480fdf8STom Rini gpmc,wait-on-write = "true"; 5231480fdf8STom Rini gpmc,bus-turnaround-ns = <0>; 5241480fdf8STom Rini gpmc,cycle2cycle-delay-ns = <0>; 5251480fdf8STom Rini gpmc,clk-activation-ns = <0>; 5261480fdf8STom Rini gpmc,wait-monitoring-ns = <0>; 5271480fdf8STom Rini gpmc,wr-access-ns = <40>; 5281480fdf8STom Rini gpmc,wr-data-mux-bus-ns = <0>; 5291480fdf8STom Rini /* MTD partition table */ 5301480fdf8STom Rini /* All SPL-* partitions are sized to minimal length 5311480fdf8STom Rini * which can be independently programmable. For 5321480fdf8STom Rini * NAND flash this is equal to size of erase-block */ 5331480fdf8STom Rini #address-cells = <1>; 5341480fdf8STom Rini #size-cells = <1>; 5351480fdf8STom Rini partition@0 { 5361480fdf8STom Rini label = "NAND.SPL"; 5371480fdf8STom Rini reg = <0x00000000 0x000020000>; 5381480fdf8STom Rini }; 5391480fdf8STom Rini partition@1 { 5401480fdf8STom Rini label = "NAND.SPL.backup1"; 5411480fdf8STom Rini reg = <0x00020000 0x00020000>; 5421480fdf8STom Rini }; 5431480fdf8STom Rini partition@2 { 5441480fdf8STom Rini label = "NAND.SPL.backup2"; 5451480fdf8STom Rini reg = <0x00040000 0x00020000>; 5461480fdf8STom Rini }; 5471480fdf8STom Rini partition@3 { 5481480fdf8STom Rini label = "NAND.SPL.backup3"; 5491480fdf8STom Rini reg = <0x00060000 0x00020000>; 5501480fdf8STom Rini }; 5511480fdf8STom Rini partition@4 { 5521480fdf8STom Rini label = "NAND.u-boot-spl-os"; 5531480fdf8STom Rini reg = <0x00080000 0x00040000>; 5541480fdf8STom Rini }; 5551480fdf8STom Rini partition@5 { 5561480fdf8STom Rini label = "NAND.u-boot"; 5571480fdf8STom Rini reg = <0x000C0000 0x00100000>; 5581480fdf8STom Rini }; 5591480fdf8STom Rini partition@6 { 5601480fdf8STom Rini label = "NAND.u-boot-env"; 5611480fdf8STom Rini reg = <0x001C0000 0x00020000>; 5621480fdf8STom Rini }; 5631480fdf8STom Rini partition@7 { 5641480fdf8STom Rini label = "NAND.u-boot-env.backup1"; 5651480fdf8STom Rini reg = <0x001E0000 0x00020000>; 5661480fdf8STom Rini }; 5671480fdf8STom Rini partition@8 { 5681480fdf8STom Rini label = "NAND.kernel"; 5691480fdf8STom Rini reg = <0x00200000 0x00800000>; 5701480fdf8STom Rini }; 5711480fdf8STom Rini partition@9 { 5721480fdf8STom Rini label = "NAND.file-system"; 5731480fdf8STom Rini reg = <0x00A00000 0x0F600000>; 5741480fdf8STom Rini }; 5751480fdf8STom Rini }; 5761480fdf8STom Rini}; 5771480fdf8STom Rini 5781480fdf8STom Rini#include "tps65910.dtsi" 5791480fdf8STom Rini 5801480fdf8STom Rini&mcasp1 { 5811480fdf8STom Rini pinctrl-names = "default"; 5821480fdf8STom Rini pinctrl-0 = <&am335x_evm_audio_pins>; 5831480fdf8STom Rini 5841480fdf8STom Rini status = "okay"; 5851480fdf8STom Rini 5861480fdf8STom Rini op-mode = <0>; /* MCASP_IIS_MODE */ 5871480fdf8STom Rini tdm-slots = <2>; 5881480fdf8STom Rini /* 4 serializers */ 5891480fdf8STom Rini serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 5901480fdf8STom Rini 0 0 1 2 5911480fdf8STom Rini >; 5921480fdf8STom Rini tx-num-evt = <32>; 5931480fdf8STom Rini rx-num-evt = <32>; 5941480fdf8STom Rini}; 5951480fdf8STom Rini 5961480fdf8STom Rini&tps { 5971480fdf8STom Rini vcc1-supply = <&vbat>; 5981480fdf8STom Rini vcc2-supply = <&vbat>; 5991480fdf8STom Rini vcc3-supply = <&vbat>; 6001480fdf8STom Rini vcc4-supply = <&vbat>; 6011480fdf8STom Rini vcc5-supply = <&vbat>; 6021480fdf8STom Rini vcc6-supply = <&vbat>; 6031480fdf8STom Rini vcc7-supply = <&vbat>; 6041480fdf8STom Rini vccio-supply = <&vbat>; 6051480fdf8STom Rini 6061480fdf8STom Rini regulators { 6071480fdf8STom Rini vrtc_reg: regulator@0 { 6081480fdf8STom Rini regulator-always-on; 6091480fdf8STom Rini }; 6101480fdf8STom Rini 6111480fdf8STom Rini vio_reg: regulator@1 { 6121480fdf8STom Rini regulator-always-on; 6131480fdf8STom Rini }; 6141480fdf8STom Rini 6151480fdf8STom Rini vdd1_reg: regulator@2 { 6161480fdf8STom Rini /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 6171480fdf8STom Rini regulator-name = "vdd_mpu"; 6181480fdf8STom Rini regulator-min-microvolt = <912500>; 6191480fdf8STom Rini regulator-max-microvolt = <1312500>; 6201480fdf8STom Rini regulator-boot-on; 6211480fdf8STom Rini regulator-always-on; 6221480fdf8STom Rini }; 6231480fdf8STom Rini 6241480fdf8STom Rini vdd2_reg: regulator@3 { 6251480fdf8STom Rini /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 6261480fdf8STom Rini regulator-name = "vdd_core"; 6271480fdf8STom Rini regulator-min-microvolt = <912500>; 6281480fdf8STom Rini regulator-max-microvolt = <1150000>; 6291480fdf8STom Rini regulator-boot-on; 6301480fdf8STom Rini regulator-always-on; 6311480fdf8STom Rini }; 6321480fdf8STom Rini 6331480fdf8STom Rini vdd3_reg: regulator@4 { 6341480fdf8STom Rini regulator-always-on; 6351480fdf8STom Rini }; 6361480fdf8STom Rini 6371480fdf8STom Rini vdig1_reg: regulator@5 { 6381480fdf8STom Rini regulator-always-on; 6391480fdf8STom Rini }; 6401480fdf8STom Rini 6411480fdf8STom Rini vdig2_reg: regulator@6 { 6421480fdf8STom Rini regulator-always-on; 6431480fdf8STom Rini }; 6441480fdf8STom Rini 6451480fdf8STom Rini vpll_reg: regulator@7 { 6461480fdf8STom Rini regulator-always-on; 6471480fdf8STom Rini }; 6481480fdf8STom Rini 6491480fdf8STom Rini vdac_reg: regulator@8 { 6501480fdf8STom Rini regulator-always-on; 6511480fdf8STom Rini }; 6521480fdf8STom Rini 6531480fdf8STom Rini vaux1_reg: regulator@9 { 6541480fdf8STom Rini regulator-always-on; 6551480fdf8STom Rini }; 6561480fdf8STom Rini 6571480fdf8STom Rini vaux2_reg: regulator@10 { 6581480fdf8STom Rini regulator-always-on; 6591480fdf8STom Rini }; 6601480fdf8STom Rini 6611480fdf8STom Rini vaux33_reg: regulator@11 { 6621480fdf8STom Rini regulator-always-on; 6631480fdf8STom Rini }; 6641480fdf8STom Rini 6651480fdf8STom Rini vmmc_reg: regulator@12 { 6661480fdf8STom Rini regulator-min-microvolt = <1800000>; 6671480fdf8STom Rini regulator-max-microvolt = <3300000>; 6681480fdf8STom Rini regulator-always-on; 6691480fdf8STom Rini }; 6701480fdf8STom Rini }; 6711480fdf8STom Rini}; 6721480fdf8STom Rini 6731480fdf8STom Rini&mac { 6741480fdf8STom Rini pinctrl-names = "default", "sleep"; 6751480fdf8STom Rini pinctrl-0 = <&cpsw_default>; 6761480fdf8STom Rini pinctrl-1 = <&cpsw_sleep>; 6771480fdf8STom Rini status = "okay"; 6781480fdf8STom Rini}; 6791480fdf8STom Rini 6801480fdf8STom Rini&davinci_mdio { 6811480fdf8STom Rini pinctrl-names = "default", "sleep"; 6821480fdf8STom Rini pinctrl-0 = <&davinci_mdio_default>; 6831480fdf8STom Rini pinctrl-1 = <&davinci_mdio_sleep>; 6841480fdf8STom Rini status = "okay"; 6851480fdf8STom Rini}; 6861480fdf8STom Rini 6871480fdf8STom Rini&cpsw_emac0 { 6881480fdf8STom Rini phy_id = <&davinci_mdio>, <0>; 6891480fdf8STom Rini phy-mode = "rgmii-txid"; 6901480fdf8STom Rini}; 6911480fdf8STom Rini 6921480fdf8STom Rini&cpsw_emac1 { 6931480fdf8STom Rini phy_id = <&davinci_mdio>, <1>; 6941480fdf8STom Rini phy-mode = "rgmii-txid"; 6951480fdf8STom Rini}; 6961480fdf8STom Rini 6971480fdf8STom Rini&tscadc { 6981480fdf8STom Rini status = "okay"; 6991480fdf8STom Rini tsc { 7001480fdf8STom Rini ti,wires = <4>; 7011480fdf8STom Rini ti,x-plate-resistance = <200>; 7021480fdf8STom Rini ti,coordinate-readouts = <5>; 7031480fdf8STom Rini ti,wire-config = <0x00 0x11 0x22 0x33>; 7041480fdf8STom Rini ti,charge-delay = <0x400>; 7051480fdf8STom Rini }; 7061480fdf8STom Rini 7071480fdf8STom Rini adc { 7081480fdf8STom Rini ti,adc-channels = <4 5 6 7>; 7091480fdf8STom Rini }; 7101480fdf8STom Rini}; 7111480fdf8STom Rini 7121480fdf8STom Rini&mmc1 { 7131480fdf8STom Rini status = "okay"; 7141480fdf8STom Rini vmmc-supply = <&vmmc_reg>; 7151480fdf8STom Rini bus-width = <4>; 7161480fdf8STom Rini pinctrl-names = "default"; 7171480fdf8STom Rini pinctrl-0 = <&mmc1_pins>; 7182c6485bcSMugunthan V N cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 7191480fdf8STom Rini}; 7201480fdf8STom Rini 7211480fdf8STom Rini&mmc3 { 7221480fdf8STom Rini /* these are on the crossbar and are outlined in the 7231480fdf8STom Rini xbar-event-map element */ 724*fdce9d35SFelix Brack dmas = <&edma 12 0 725*fdce9d35SFelix Brack &edma 13 0>; 7261480fdf8STom Rini dma-names = "tx", "rx"; 7271480fdf8STom Rini status = "okay"; 7281480fdf8STom Rini vmmc-supply = <&wlan_en_reg>; 7291480fdf8STom Rini bus-width = <4>; 7301480fdf8STom Rini pinctrl-names = "default"; 7311480fdf8STom Rini pinctrl-0 = <&mmc3_pins &wlan_pins>; 7321480fdf8STom Rini ti,non-removable; 7331480fdf8STom Rini ti,needs-special-hs-handling; 7341480fdf8STom Rini cap-power-off-card; 7351480fdf8STom Rini keep-power-in-suspend; 7361480fdf8STom Rini 7371480fdf8STom Rini #address-cells = <1>; 7381480fdf8STom Rini #size-cells = <0>; 7391480fdf8STom Rini wlcore: wlcore@0 { 7401480fdf8STom Rini compatible = "ti,wl1835"; 7411480fdf8STom Rini reg = <2>; 7421480fdf8STom Rini interrupt-parent = <&gpio3>; 7431480fdf8STom Rini interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 7441480fdf8STom Rini }; 7451480fdf8STom Rini}; 7461480fdf8STom Rini 7471480fdf8STom Rini&edma { 7481480fdf8STom Rini ti,edma-xbar-event-map = /bits/ 16 <1 12 7491480fdf8STom Rini 2 13>; 7501480fdf8STom Rini}; 7511480fdf8STom Rini 7521480fdf8STom Rini&sham { 7531480fdf8STom Rini status = "okay"; 7541480fdf8STom Rini}; 7551480fdf8STom Rini 7561480fdf8STom Rini&aes { 7571480fdf8STom Rini status = "okay"; 7581480fdf8STom Rini}; 7591480fdf8STom Rini 7601480fdf8STom Rini&dcan1 { 7611480fdf8STom Rini status = "disabled"; /* Enable only if Profile 1 is selected */ 7621480fdf8STom Rini pinctrl-names = "default"; 7631480fdf8STom Rini pinctrl-0 = <&dcan1_pins_default>; 7641480fdf8STom Rini}; 765