xref: /openbmc/u-boot/arch/arm/dts/am335x-evm.dts (revision 1480fdf8)
1*1480fdf8STom Rini/*
2*1480fdf8STom Rini * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3*1480fdf8STom Rini *
4*1480fdf8STom Rini * This program is free software; you can redistribute it and/or modify
5*1480fdf8STom Rini * it under the terms of the GNU General Public License version 2 as
6*1480fdf8STom Rini * published by the Free Software Foundation.
7*1480fdf8STom Rini */
8*1480fdf8STom Rini/dts-v1/;
9*1480fdf8STom Rini
10*1480fdf8STom Rini#include "am33xx.dtsi"
11*1480fdf8STom Rini#include <dt-bindings/interrupt-controller/irq.h>
12*1480fdf8STom Rini
13*1480fdf8STom Rini/ {
14*1480fdf8STom Rini	model = "TI AM335x EVM";
15*1480fdf8STom Rini	compatible = "ti,am335x-evm", "ti,am33xx";
16*1480fdf8STom Rini
17*1480fdf8STom Rini	chosen {
18*1480fdf8STom Rini		stdout-path = &uart0;
19*1480fdf8STom Rini	};
20*1480fdf8STom Rini
21*1480fdf8STom Rini	cpus {
22*1480fdf8STom Rini		cpu@0 {
23*1480fdf8STom Rini			cpu0-supply = <&vdd1_reg>;
24*1480fdf8STom Rini		};
25*1480fdf8STom Rini	};
26*1480fdf8STom Rini
27*1480fdf8STom Rini	memory {
28*1480fdf8STom Rini		device_type = "memory";
29*1480fdf8STom Rini		reg = <0x80000000 0x10000000>; /* 256 MB */
30*1480fdf8STom Rini	};
31*1480fdf8STom Rini
32*1480fdf8STom Rini	vbat: fixedregulator@0 {
33*1480fdf8STom Rini		compatible = "regulator-fixed";
34*1480fdf8STom Rini		regulator-name = "vbat";
35*1480fdf8STom Rini		regulator-min-microvolt = <5000000>;
36*1480fdf8STom Rini		regulator-max-microvolt = <5000000>;
37*1480fdf8STom Rini		regulator-boot-on;
38*1480fdf8STom Rini	};
39*1480fdf8STom Rini
40*1480fdf8STom Rini	lis3_reg: fixedregulator@1 {
41*1480fdf8STom Rini		compatible = "regulator-fixed";
42*1480fdf8STom Rini		regulator-name = "lis3_reg";
43*1480fdf8STom Rini		regulator-boot-on;
44*1480fdf8STom Rini	};
45*1480fdf8STom Rini
46*1480fdf8STom Rini	wlan_en_reg: fixedregulator@2 {
47*1480fdf8STom Rini		compatible = "regulator-fixed";
48*1480fdf8STom Rini		regulator-name = "wlan-en-regulator";
49*1480fdf8STom Rini		regulator-min-microvolt = <1800000>;
50*1480fdf8STom Rini		regulator-max-microvolt = <1800000>;
51*1480fdf8STom Rini
52*1480fdf8STom Rini		/* WLAN_EN GPIO for this board - Bank1, pin16 */
53*1480fdf8STom Rini		gpio = <&gpio1 16 0>;
54*1480fdf8STom Rini
55*1480fdf8STom Rini		/* WLAN card specific delay */
56*1480fdf8STom Rini		startup-delay-us = <70000>;
57*1480fdf8STom Rini		enable-active-high;
58*1480fdf8STom Rini	};
59*1480fdf8STom Rini
60*1480fdf8STom Rini	matrix_keypad: matrix_keypad@0 {
61*1480fdf8STom Rini		compatible = "gpio-matrix-keypad";
62*1480fdf8STom Rini		debounce-delay-ms = <5>;
63*1480fdf8STom Rini		col-scan-delay-us = <2>;
64*1480fdf8STom Rini
65*1480fdf8STom Rini		row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH		/* Bank1, pin25 */
66*1480fdf8STom Rini			     &gpio1 26 GPIO_ACTIVE_HIGH		/* Bank1, pin26 */
67*1480fdf8STom Rini			     &gpio1 27 GPIO_ACTIVE_HIGH>;	/* Bank1, pin27 */
68*1480fdf8STom Rini
69*1480fdf8STom Rini		col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH		/* Bank1, pin21 */
70*1480fdf8STom Rini			     &gpio1 22 GPIO_ACTIVE_HIGH>;	/* Bank1, pin22 */
71*1480fdf8STom Rini
72*1480fdf8STom Rini		linux,keymap = <0x0000008b	/* MENU */
73*1480fdf8STom Rini				0x0100009e	/* BACK */
74*1480fdf8STom Rini				0x02000069	/* LEFT */
75*1480fdf8STom Rini				0x0001006a	/* RIGHT */
76*1480fdf8STom Rini				0x0101001c	/* ENTER */
77*1480fdf8STom Rini				0x0201006c>;	/* DOWN */
78*1480fdf8STom Rini	};
79*1480fdf8STom Rini
80*1480fdf8STom Rini	gpio_keys: volume_keys@0 {
81*1480fdf8STom Rini		compatible = "gpio-keys";
82*1480fdf8STom Rini		#address-cells = <1>;
83*1480fdf8STom Rini		#size-cells = <0>;
84*1480fdf8STom Rini		autorepeat;
85*1480fdf8STom Rini
86*1480fdf8STom Rini		switch@9 {
87*1480fdf8STom Rini			label = "volume-up";
88*1480fdf8STom Rini			linux,code = <115>;
89*1480fdf8STom Rini			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
90*1480fdf8STom Rini			gpio-key,wakeup;
91*1480fdf8STom Rini		};
92*1480fdf8STom Rini
93*1480fdf8STom Rini		switch@10 {
94*1480fdf8STom Rini			label = "volume-down";
95*1480fdf8STom Rini			linux,code = <114>;
96*1480fdf8STom Rini			gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
97*1480fdf8STom Rini			gpio-key,wakeup;
98*1480fdf8STom Rini		};
99*1480fdf8STom Rini	};
100*1480fdf8STom Rini
101*1480fdf8STom Rini	backlight {
102*1480fdf8STom Rini		compatible = "pwm-backlight";
103*1480fdf8STom Rini		pwms = <&ecap0 0 50000 0>;
104*1480fdf8STom Rini		brightness-levels = <0 51 53 56 62 75 101 152 255>;
105*1480fdf8STom Rini		default-brightness-level = <8>;
106*1480fdf8STom Rini	};
107*1480fdf8STom Rini
108*1480fdf8STom Rini	panel {
109*1480fdf8STom Rini		compatible = "ti,tilcdc,panel";
110*1480fdf8STom Rini		status = "okay";
111*1480fdf8STom Rini		pinctrl-names = "default";
112*1480fdf8STom Rini		pinctrl-0 = <&lcd_pins_s0>;
113*1480fdf8STom Rini		panel-info {
114*1480fdf8STom Rini			ac-bias           = <255>;
115*1480fdf8STom Rini			ac-bias-intrpt    = <0>;
116*1480fdf8STom Rini			dma-burst-sz      = <16>;
117*1480fdf8STom Rini			bpp               = <32>;
118*1480fdf8STom Rini			fdd               = <0x80>;
119*1480fdf8STom Rini			sync-edge         = <0>;
120*1480fdf8STom Rini			sync-ctrl         = <1>;
121*1480fdf8STom Rini			raster-order      = <0>;
122*1480fdf8STom Rini			fifo-th           = <0>;
123*1480fdf8STom Rini		};
124*1480fdf8STom Rini
125*1480fdf8STom Rini		display-timings {
126*1480fdf8STom Rini			800x480p62 {
127*1480fdf8STom Rini				clock-frequency = <30000000>;
128*1480fdf8STom Rini				hactive = <800>;
129*1480fdf8STom Rini				vactive = <480>;
130*1480fdf8STom Rini				hfront-porch = <39>;
131*1480fdf8STom Rini				hback-porch = <39>;
132*1480fdf8STom Rini				hsync-len = <47>;
133*1480fdf8STom Rini				vback-porch = <29>;
134*1480fdf8STom Rini				vfront-porch = <13>;
135*1480fdf8STom Rini				vsync-len = <2>;
136*1480fdf8STom Rini				hsync-active = <1>;
137*1480fdf8STom Rini				vsync-active = <1>;
138*1480fdf8STom Rini			};
139*1480fdf8STom Rini		};
140*1480fdf8STom Rini	};
141*1480fdf8STom Rini
142*1480fdf8STom Rini	sound {
143*1480fdf8STom Rini		compatible = "ti,da830-evm-audio";
144*1480fdf8STom Rini		ti,model = "AM335x-EVM";
145*1480fdf8STom Rini		ti,audio-codec = <&tlv320aic3106>;
146*1480fdf8STom Rini		ti,mcasp-controller = <&mcasp1>;
147*1480fdf8STom Rini		ti,codec-clock-rate = <12000000>;
148*1480fdf8STom Rini		ti,audio-routing =
149*1480fdf8STom Rini			"Headphone Jack",       "HPLOUT",
150*1480fdf8STom Rini			"Headphone Jack",       "HPROUT",
151*1480fdf8STom Rini			"LINE1L",               "Line In",
152*1480fdf8STom Rini			"LINE1R",               "Line In";
153*1480fdf8STom Rini	};
154*1480fdf8STom Rini};
155*1480fdf8STom Rini
156*1480fdf8STom Rini&am33xx_pinmux {
157*1480fdf8STom Rini	pinctrl-names = "default";
158*1480fdf8STom Rini	pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
159*1480fdf8STom Rini
160*1480fdf8STom Rini	matrix_keypad_s0: matrix_keypad_s0 {
161*1480fdf8STom Rini		pinctrl-single,pins = <
162*1480fdf8STom Rini			0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a5.gpio1_21 */
163*1480fdf8STom Rini			0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a6.gpio1_22 */
164*1480fdf8STom Rini			0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a9.gpio1_25 */
165*1480fdf8STom Rini			0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a10.gpio1_26 */
166*1480fdf8STom Rini			0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a11.gpio1_27 */
167*1480fdf8STom Rini		>;
168*1480fdf8STom Rini	};
169*1480fdf8STom Rini
170*1480fdf8STom Rini	volume_keys_s0: volume_keys_s0 {
171*1480fdf8STom Rini		pinctrl-single,pins = <
172*1480fdf8STom Rini			0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* spi0_sclk.gpio0_2 */
173*1480fdf8STom Rini			0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)	/* spi0_d0.gpio0_3 */
174*1480fdf8STom Rini		>;
175*1480fdf8STom Rini	};
176*1480fdf8STom Rini
177*1480fdf8STom Rini	i2c0_pins: pinmux_i2c0_pins {
178*1480fdf8STom Rini		pinctrl-single,pins = <
179*1480fdf8STom Rini			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
180*1480fdf8STom Rini			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
181*1480fdf8STom Rini		>;
182*1480fdf8STom Rini	};
183*1480fdf8STom Rini
184*1480fdf8STom Rini	i2c1_pins: pinmux_i2c1_pins {
185*1480fdf8STom Rini		pinctrl-single,pins = <
186*1480fdf8STom Rini			0x158 (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_d1.i2c1_sda */
187*1480fdf8STom Rini			0x15c (PIN_INPUT_PULLUP | MUX_MODE2)	/* spi0_cs0.i2c1_scl */
188*1480fdf8STom Rini		>;
189*1480fdf8STom Rini	};
190*1480fdf8STom Rini
191*1480fdf8STom Rini	uart0_pins: pinmux_uart0_pins {
192*1480fdf8STom Rini		pinctrl-single,pins = <
193*1480fdf8STom Rini			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart0_rxd.uart0_rxd */
194*1480fdf8STom Rini			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart0_txd.uart0_txd */
195*1480fdf8STom Rini		>;
196*1480fdf8STom Rini	};
197*1480fdf8STom Rini
198*1480fdf8STom Rini	uart1_pins: pinmux_uart1_pins {
199*1480fdf8STom Rini		pinctrl-single,pins = <
200*1480fdf8STom Rini			0x178 (PIN_INPUT | MUX_MODE0)		/* uart1_ctsn.uart1_ctsn */
201*1480fdf8STom Rini			0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_rtsn.uart1_rtsn */
202*1480fdf8STom Rini			0x180 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
203*1480fdf8STom Rini			0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
204*1480fdf8STom Rini		>;
205*1480fdf8STom Rini	};
206*1480fdf8STom Rini
207*1480fdf8STom Rini	clkout2_pin: pinmux_clkout2_pin {
208*1480fdf8STom Rini		pinctrl-single,pins = <
209*1480fdf8STom Rini			0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)	/* xdma_event_intr1.clkout2 */
210*1480fdf8STom Rini		>;
211*1480fdf8STom Rini	};
212*1480fdf8STom Rini
213*1480fdf8STom Rini	nandflash_pins_s0: nandflash_pins_s0 {
214*1480fdf8STom Rini		pinctrl-single,pins = <
215*1480fdf8STom Rini			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
216*1480fdf8STom Rini			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
217*1480fdf8STom Rini			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
218*1480fdf8STom Rini			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
219*1480fdf8STom Rini			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
220*1480fdf8STom Rini			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
221*1480fdf8STom Rini			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
222*1480fdf8STom Rini			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
223*1480fdf8STom Rini			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
224*1480fdf8STom Rini			0x74 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpmc_wpn.gpio0_30 */
225*1480fdf8STom Rini			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
226*1480fdf8STom Rini			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
227*1480fdf8STom Rini			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
228*1480fdf8STom Rini			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
229*1480fdf8STom Rini			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
230*1480fdf8STom Rini		>;
231*1480fdf8STom Rini	};
232*1480fdf8STom Rini
233*1480fdf8STom Rini	ecap0_pins: backlight_pins {
234*1480fdf8STom Rini		pinctrl-single,pins = <
235*1480fdf8STom Rini			0x164 0x0	/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
236*1480fdf8STom Rini		>;
237*1480fdf8STom Rini	};
238*1480fdf8STom Rini
239*1480fdf8STom Rini	cpsw_default: cpsw_default {
240*1480fdf8STom Rini		pinctrl-single,pins = <
241*1480fdf8STom Rini			/* Slave 1 */
242*1480fdf8STom Rini			0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txen.rgmii1_tctl */
243*1480fdf8STom Rini			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxdv.rgmii1_rctl */
244*1480fdf8STom Rini			0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd3.rgmii1_td3 */
245*1480fdf8STom Rini			0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd2.rgmii1_td2 */
246*1480fdf8STom Rini			0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd1.rgmii1_td1 */
247*1480fdf8STom Rini			0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txd0.rgmii1_td0 */
248*1480fdf8STom Rini			0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)	/* mii1_txclk.rgmii1_tclk */
249*1480fdf8STom Rini			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxclk.rgmii1_rclk */
250*1480fdf8STom Rini			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd3.rgmii1_rd3 */
251*1480fdf8STom Rini			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd2.rgmii1_rd2 */
252*1480fdf8STom Rini			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd1.rgmii1_rd1 */
253*1480fdf8STom Rini			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)	/* mii1_rxd0.rgmii1_rd0 */
254*1480fdf8STom Rini		>;
255*1480fdf8STom Rini	};
256*1480fdf8STom Rini
257*1480fdf8STom Rini	cpsw_sleep: cpsw_sleep {
258*1480fdf8STom Rini		pinctrl-single,pins = <
259*1480fdf8STom Rini			/* Slave 1 reset value */
260*1480fdf8STom Rini			0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
261*1480fdf8STom Rini			0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
262*1480fdf8STom Rini			0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
263*1480fdf8STom Rini			0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
264*1480fdf8STom Rini			0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
265*1480fdf8STom Rini			0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
266*1480fdf8STom Rini			0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
267*1480fdf8STom Rini			0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
268*1480fdf8STom Rini			0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
269*1480fdf8STom Rini			0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
270*1480fdf8STom Rini			0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
271*1480fdf8STom Rini			0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
272*1480fdf8STom Rini		>;
273*1480fdf8STom Rini	};
274*1480fdf8STom Rini
275*1480fdf8STom Rini	davinci_mdio_default: davinci_mdio_default {
276*1480fdf8STom Rini		pinctrl-single,pins = <
277*1480fdf8STom Rini			/* MDIO */
278*1480fdf8STom Rini			0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
279*1480fdf8STom Rini			0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
280*1480fdf8STom Rini		>;
281*1480fdf8STom Rini	};
282*1480fdf8STom Rini
283*1480fdf8STom Rini	davinci_mdio_sleep: davinci_mdio_sleep {
284*1480fdf8STom Rini		pinctrl-single,pins = <
285*1480fdf8STom Rini			/* MDIO reset value */
286*1480fdf8STom Rini			0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
287*1480fdf8STom Rini			0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
288*1480fdf8STom Rini		>;
289*1480fdf8STom Rini	};
290*1480fdf8STom Rini
291*1480fdf8STom Rini	mmc1_pins: pinmux_mmc1_pins {
292*1480fdf8STom Rini		pinctrl-single,pins = <
293*1480fdf8STom Rini			0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
294*1480fdf8STom Rini		>;
295*1480fdf8STom Rini	};
296*1480fdf8STom Rini
297*1480fdf8STom Rini	mmc3_pins: pinmux_mmc3_pins {
298*1480fdf8STom Rini		pinctrl-single,pins = <
299*1480fdf8STom Rini			0x44 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
300*1480fdf8STom Rini			0x48 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
301*1480fdf8STom Rini			0x4C (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
302*1480fdf8STom Rini			0x78 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
303*1480fdf8STom Rini			0x88 (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
304*1480fdf8STom Rini			0x8C (PIN_INPUT_PULLUP | MUX_MODE3)	/* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
305*1480fdf8STom Rini		>;
306*1480fdf8STom Rini	};
307*1480fdf8STom Rini
308*1480fdf8STom Rini	wlan_pins: pinmux_wlan_pins {
309*1480fdf8STom Rini		pinctrl-single,pins = <
310*1480fdf8STom Rini			0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* gpmc_a0.gpio1_16 */
311*1480fdf8STom Rini			0x19C (PIN_INPUT | MUX_MODE7)		/* mcasp0_ahclkr.gpio3_17 */
312*1480fdf8STom Rini			0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mcasp0_ahclkx.gpio3_21 */
313*1480fdf8STom Rini		>;
314*1480fdf8STom Rini	};
315*1480fdf8STom Rini
316*1480fdf8STom Rini	lcd_pins_s0: lcd_pins_s0 {
317*1480fdf8STom Rini		pinctrl-single,pins = <
318*1480fdf8STom Rini			0x20 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad8.lcd_data23 */
319*1480fdf8STom Rini			0x24 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad9.lcd_data22 */
320*1480fdf8STom Rini			0x28 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad10.lcd_data21 */
321*1480fdf8STom Rini			0x2c (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad11.lcd_data20 */
322*1480fdf8STom Rini			0x30 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad12.lcd_data19 */
323*1480fdf8STom Rini			0x34 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad13.lcd_data18 */
324*1480fdf8STom Rini			0x38 (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad14.lcd_data17 */
325*1480fdf8STom Rini			0x3c (PIN_OUTPUT | MUX_MODE1)		/* gpmc_ad15.lcd_data16 */
326*1480fdf8STom Rini			0xa0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data0.lcd_data0 */
327*1480fdf8STom Rini			0xa4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data1.lcd_data1 */
328*1480fdf8STom Rini			0xa8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data2.lcd_data2 */
329*1480fdf8STom Rini			0xac (PIN_OUTPUT | MUX_MODE0)		/* lcd_data3.lcd_data3 */
330*1480fdf8STom Rini			0xb0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data4.lcd_data4 */
331*1480fdf8STom Rini			0xb4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data5.lcd_data5 */
332*1480fdf8STom Rini			0xb8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data6.lcd_data6 */
333*1480fdf8STom Rini			0xbc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data7.lcd_data7 */
334*1480fdf8STom Rini			0xc0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data8.lcd_data8 */
335*1480fdf8STom Rini			0xc4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data9.lcd_data9 */
336*1480fdf8STom Rini			0xc8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data10.lcd_data10 */
337*1480fdf8STom Rini			0xcc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data11.lcd_data11 */
338*1480fdf8STom Rini			0xd0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data12.lcd_data12 */
339*1480fdf8STom Rini			0xd4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data13.lcd_data13 */
340*1480fdf8STom Rini			0xd8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_data14.lcd_data14 */
341*1480fdf8STom Rini			0xdc (PIN_OUTPUT | MUX_MODE0)		/* lcd_data15.lcd_data15 */
342*1480fdf8STom Rini			0xe0 (PIN_OUTPUT | MUX_MODE0)		/* lcd_vsync.lcd_vsync */
343*1480fdf8STom Rini			0xe4 (PIN_OUTPUT | MUX_MODE0)		/* lcd_hsync.lcd_hsync */
344*1480fdf8STom Rini			0xe8 (PIN_OUTPUT | MUX_MODE0)		/* lcd_pclk.lcd_pclk */
345*1480fdf8STom Rini			0xec (PIN_OUTPUT | MUX_MODE0)		/* lcd_ac_bias_en.lcd_ac_bias_en */
346*1480fdf8STom Rini		>;
347*1480fdf8STom Rini	};
348*1480fdf8STom Rini
349*1480fdf8STom Rini	am335x_evm_audio_pins: am335x_evm_audio_pins {
350*1480fdf8STom Rini		pinctrl-single,pins = <
351*1480fdf8STom Rini			0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
352*1480fdf8STom Rini			0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
353*1480fdf8STom Rini			0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
354*1480fdf8STom Rini			0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
355*1480fdf8STom Rini		>;
356*1480fdf8STom Rini	};
357*1480fdf8STom Rini
358*1480fdf8STom Rini	dcan1_pins_default: dcan1_pins_default {
359*1480fdf8STom Rini		pinctrl-single,pins = <
360*1480fdf8STom Rini			0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
361*1480fdf8STom Rini			0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
362*1480fdf8STom Rini		>;
363*1480fdf8STom Rini	};
364*1480fdf8STom Rini};
365*1480fdf8STom Rini
366*1480fdf8STom Rini&uart0 {
367*1480fdf8STom Rini	pinctrl-names = "default";
368*1480fdf8STom Rini	pinctrl-0 = <&uart0_pins>;
369*1480fdf8STom Rini
370*1480fdf8STom Rini	status = "okay";
371*1480fdf8STom Rini};
372*1480fdf8STom Rini
373*1480fdf8STom Rini&uart1 {
374*1480fdf8STom Rini	pinctrl-names = "default";
375*1480fdf8STom Rini	pinctrl-0 = <&uart1_pins>;
376*1480fdf8STom Rini
377*1480fdf8STom Rini	status = "okay";
378*1480fdf8STom Rini};
379*1480fdf8STom Rini
380*1480fdf8STom Rini&i2c0 {
381*1480fdf8STom Rini	pinctrl-names = "default";
382*1480fdf8STom Rini	pinctrl-0 = <&i2c0_pins>;
383*1480fdf8STom Rini
384*1480fdf8STom Rini	status = "okay";
385*1480fdf8STom Rini	clock-frequency = <400000>;
386*1480fdf8STom Rini
387*1480fdf8STom Rini	tps: tps@2d {
388*1480fdf8STom Rini		reg = <0x2d>;
389*1480fdf8STom Rini	};
390*1480fdf8STom Rini};
391*1480fdf8STom Rini
392*1480fdf8STom Rini&usb {
393*1480fdf8STom Rini	status = "okay";
394*1480fdf8STom Rini};
395*1480fdf8STom Rini
396*1480fdf8STom Rini&usb_ctrl_mod {
397*1480fdf8STom Rini	status = "okay";
398*1480fdf8STom Rini};
399*1480fdf8STom Rini
400*1480fdf8STom Rini&usb0_phy {
401*1480fdf8STom Rini	status = "okay";
402*1480fdf8STom Rini};
403*1480fdf8STom Rini
404*1480fdf8STom Rini&usb1_phy {
405*1480fdf8STom Rini	status = "okay";
406*1480fdf8STom Rini};
407*1480fdf8STom Rini
408*1480fdf8STom Rini&usb0 {
409*1480fdf8STom Rini	status = "okay";
410*1480fdf8STom Rini};
411*1480fdf8STom Rini
412*1480fdf8STom Rini&usb1 {
413*1480fdf8STom Rini	status = "okay";
414*1480fdf8STom Rini	dr_mode = "host";
415*1480fdf8STom Rini};
416*1480fdf8STom Rini
417*1480fdf8STom Rini&cppi41dma  {
418*1480fdf8STom Rini	status = "okay";
419*1480fdf8STom Rini};
420*1480fdf8STom Rini
421*1480fdf8STom Rini&i2c1 {
422*1480fdf8STom Rini	pinctrl-names = "default";
423*1480fdf8STom Rini	pinctrl-0 = <&i2c1_pins>;
424*1480fdf8STom Rini
425*1480fdf8STom Rini	status = "okay";
426*1480fdf8STom Rini	clock-frequency = <100000>;
427*1480fdf8STom Rini
428*1480fdf8STom Rini	lis331dlh: lis331dlh@18 {
429*1480fdf8STom Rini		compatible = "st,lis331dlh", "st,lis3lv02d";
430*1480fdf8STom Rini		reg = <0x18>;
431*1480fdf8STom Rini		Vdd-supply = <&lis3_reg>;
432*1480fdf8STom Rini		Vdd_IO-supply = <&lis3_reg>;
433*1480fdf8STom Rini
434*1480fdf8STom Rini		st,click-single-x;
435*1480fdf8STom Rini		st,click-single-y;
436*1480fdf8STom Rini		st,click-single-z;
437*1480fdf8STom Rini		st,click-thresh-x = <10>;
438*1480fdf8STom Rini		st,click-thresh-y = <10>;
439*1480fdf8STom Rini		st,click-thresh-z = <10>;
440*1480fdf8STom Rini		st,irq1-click;
441*1480fdf8STom Rini		st,irq2-click;
442*1480fdf8STom Rini		st,wakeup-x-lo;
443*1480fdf8STom Rini		st,wakeup-x-hi;
444*1480fdf8STom Rini		st,wakeup-y-lo;
445*1480fdf8STom Rini		st,wakeup-y-hi;
446*1480fdf8STom Rini		st,wakeup-z-lo;
447*1480fdf8STom Rini		st,wakeup-z-hi;
448*1480fdf8STom Rini		st,min-limit-x = <120>;
449*1480fdf8STom Rini		st,min-limit-y = <120>;
450*1480fdf8STom Rini		st,min-limit-z = <140>;
451*1480fdf8STom Rini		st,max-limit-x = <550>;
452*1480fdf8STom Rini		st,max-limit-y = <550>;
453*1480fdf8STom Rini		st,max-limit-z = <750>;
454*1480fdf8STom Rini	};
455*1480fdf8STom Rini
456*1480fdf8STom Rini	tsl2550: tsl2550@39 {
457*1480fdf8STom Rini		compatible = "taos,tsl2550";
458*1480fdf8STom Rini		reg = <0x39>;
459*1480fdf8STom Rini	};
460*1480fdf8STom Rini
461*1480fdf8STom Rini	tmp275: tmp275@48 {
462*1480fdf8STom Rini		compatible = "ti,tmp275";
463*1480fdf8STom Rini		reg = <0x48>;
464*1480fdf8STom Rini	};
465*1480fdf8STom Rini
466*1480fdf8STom Rini	tlv320aic3106: tlv320aic3106@1b {
467*1480fdf8STom Rini		compatible = "ti,tlv320aic3106";
468*1480fdf8STom Rini		reg = <0x1b>;
469*1480fdf8STom Rini		status = "okay";
470*1480fdf8STom Rini
471*1480fdf8STom Rini		/* Regulators */
472*1480fdf8STom Rini		AVDD-supply = <&vaux2_reg>;
473*1480fdf8STom Rini		IOVDD-supply = <&vaux2_reg>;
474*1480fdf8STom Rini		DRVDD-supply = <&vaux2_reg>;
475*1480fdf8STom Rini		DVDD-supply = <&vbat>;
476*1480fdf8STom Rini	};
477*1480fdf8STom Rini};
478*1480fdf8STom Rini
479*1480fdf8STom Rini&lcdc {
480*1480fdf8STom Rini	status = "okay";
481*1480fdf8STom Rini};
482*1480fdf8STom Rini
483*1480fdf8STom Rini&elm {
484*1480fdf8STom Rini	status = "okay";
485*1480fdf8STom Rini};
486*1480fdf8STom Rini
487*1480fdf8STom Rini&epwmss0 {
488*1480fdf8STom Rini	status = "okay";
489*1480fdf8STom Rini
490*1480fdf8STom Rini	ecap0: ecap@48300100 {
491*1480fdf8STom Rini		status = "okay";
492*1480fdf8STom Rini		pinctrl-names = "default";
493*1480fdf8STom Rini		pinctrl-0 = <&ecap0_pins>;
494*1480fdf8STom Rini	};
495*1480fdf8STom Rini};
496*1480fdf8STom Rini
497*1480fdf8STom Rini&gpmc {
498*1480fdf8STom Rini	status = "okay";
499*1480fdf8STom Rini	pinctrl-names = "default";
500*1480fdf8STom Rini	pinctrl-0 = <&nandflash_pins_s0>;
501*1480fdf8STom Rini	ranges = <0 0 0x08000000 0x1000000>;	/* CS0: 16MB for NAND */
502*1480fdf8STom Rini	nand@0,0 {
503*1480fdf8STom Rini		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
504*1480fdf8STom Rini		ti,nand-ecc-opt = "bch8";
505*1480fdf8STom Rini		ti,elm-id = <&elm>;
506*1480fdf8STom Rini		nand-bus-width = <8>;
507*1480fdf8STom Rini		gpmc,device-width = <1>;
508*1480fdf8STom Rini		gpmc,sync-clk-ps = <0>;
509*1480fdf8STom Rini		gpmc,cs-on-ns = <0>;
510*1480fdf8STom Rini		gpmc,cs-rd-off-ns = <44>;
511*1480fdf8STom Rini		gpmc,cs-wr-off-ns = <44>;
512*1480fdf8STom Rini		gpmc,adv-on-ns = <6>;
513*1480fdf8STom Rini		gpmc,adv-rd-off-ns = <34>;
514*1480fdf8STom Rini		gpmc,adv-wr-off-ns = <44>;
515*1480fdf8STom Rini		gpmc,we-on-ns = <0>;
516*1480fdf8STom Rini		gpmc,we-off-ns = <40>;
517*1480fdf8STom Rini		gpmc,oe-on-ns = <0>;
518*1480fdf8STom Rini		gpmc,oe-off-ns = <54>;
519*1480fdf8STom Rini		gpmc,access-ns = <64>;
520*1480fdf8STom Rini		gpmc,rd-cycle-ns = <82>;
521*1480fdf8STom Rini		gpmc,wr-cycle-ns = <82>;
522*1480fdf8STom Rini		gpmc,wait-on-read = "true";
523*1480fdf8STom Rini		gpmc,wait-on-write = "true";
524*1480fdf8STom Rini		gpmc,bus-turnaround-ns = <0>;
525*1480fdf8STom Rini		gpmc,cycle2cycle-delay-ns = <0>;
526*1480fdf8STom Rini		gpmc,clk-activation-ns = <0>;
527*1480fdf8STom Rini		gpmc,wait-monitoring-ns = <0>;
528*1480fdf8STom Rini		gpmc,wr-access-ns = <40>;
529*1480fdf8STom Rini		gpmc,wr-data-mux-bus-ns = <0>;
530*1480fdf8STom Rini		/* MTD partition table */
531*1480fdf8STom Rini		/* All SPL-* partitions are sized to minimal length
532*1480fdf8STom Rini		 * which can be independently programmable. For
533*1480fdf8STom Rini		 * NAND flash this is equal to size of erase-block */
534*1480fdf8STom Rini		#address-cells = <1>;
535*1480fdf8STom Rini		#size-cells = <1>;
536*1480fdf8STom Rini		partition@0 {
537*1480fdf8STom Rini			label = "NAND.SPL";
538*1480fdf8STom Rini			reg = <0x00000000 0x000020000>;
539*1480fdf8STom Rini		};
540*1480fdf8STom Rini		partition@1 {
541*1480fdf8STom Rini			label = "NAND.SPL.backup1";
542*1480fdf8STom Rini			reg = <0x00020000 0x00020000>;
543*1480fdf8STom Rini		};
544*1480fdf8STom Rini		partition@2 {
545*1480fdf8STom Rini			label = "NAND.SPL.backup2";
546*1480fdf8STom Rini			reg = <0x00040000 0x00020000>;
547*1480fdf8STom Rini		};
548*1480fdf8STom Rini		partition@3 {
549*1480fdf8STom Rini			label = "NAND.SPL.backup3";
550*1480fdf8STom Rini			reg = <0x00060000 0x00020000>;
551*1480fdf8STom Rini		};
552*1480fdf8STom Rini		partition@4 {
553*1480fdf8STom Rini			label = "NAND.u-boot-spl-os";
554*1480fdf8STom Rini			reg = <0x00080000 0x00040000>;
555*1480fdf8STom Rini		};
556*1480fdf8STom Rini		partition@5 {
557*1480fdf8STom Rini			label = "NAND.u-boot";
558*1480fdf8STom Rini			reg = <0x000C0000 0x00100000>;
559*1480fdf8STom Rini		};
560*1480fdf8STom Rini		partition@6 {
561*1480fdf8STom Rini			label = "NAND.u-boot-env";
562*1480fdf8STom Rini			reg = <0x001C0000 0x00020000>;
563*1480fdf8STom Rini		};
564*1480fdf8STom Rini		partition@7 {
565*1480fdf8STom Rini			label = "NAND.u-boot-env.backup1";
566*1480fdf8STom Rini			reg = <0x001E0000 0x00020000>;
567*1480fdf8STom Rini		};
568*1480fdf8STom Rini		partition@8 {
569*1480fdf8STom Rini			label = "NAND.kernel";
570*1480fdf8STom Rini			reg = <0x00200000 0x00800000>;
571*1480fdf8STom Rini		};
572*1480fdf8STom Rini		partition@9 {
573*1480fdf8STom Rini			label = "NAND.file-system";
574*1480fdf8STom Rini			reg = <0x00A00000 0x0F600000>;
575*1480fdf8STom Rini		};
576*1480fdf8STom Rini	};
577*1480fdf8STom Rini};
578*1480fdf8STom Rini
579*1480fdf8STom Rini#include "tps65910.dtsi"
580*1480fdf8STom Rini
581*1480fdf8STom Rini&mcasp1 {
582*1480fdf8STom Rini		pinctrl-names = "default";
583*1480fdf8STom Rini		pinctrl-0 = <&am335x_evm_audio_pins>;
584*1480fdf8STom Rini
585*1480fdf8STom Rini		status = "okay";
586*1480fdf8STom Rini
587*1480fdf8STom Rini		op-mode = <0>;          /* MCASP_IIS_MODE */
588*1480fdf8STom Rini		tdm-slots = <2>;
589*1480fdf8STom Rini		/* 4 serializers */
590*1480fdf8STom Rini		serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
591*1480fdf8STom Rini			0 0 1 2
592*1480fdf8STom Rini		>;
593*1480fdf8STom Rini		tx-num-evt = <32>;
594*1480fdf8STom Rini		rx-num-evt = <32>;
595*1480fdf8STom Rini};
596*1480fdf8STom Rini
597*1480fdf8STom Rini&tps {
598*1480fdf8STom Rini	vcc1-supply = <&vbat>;
599*1480fdf8STom Rini	vcc2-supply = <&vbat>;
600*1480fdf8STom Rini	vcc3-supply = <&vbat>;
601*1480fdf8STom Rini	vcc4-supply = <&vbat>;
602*1480fdf8STom Rini	vcc5-supply = <&vbat>;
603*1480fdf8STom Rini	vcc6-supply = <&vbat>;
604*1480fdf8STom Rini	vcc7-supply = <&vbat>;
605*1480fdf8STom Rini	vccio-supply = <&vbat>;
606*1480fdf8STom Rini
607*1480fdf8STom Rini	regulators {
608*1480fdf8STom Rini		vrtc_reg: regulator@0 {
609*1480fdf8STom Rini			regulator-always-on;
610*1480fdf8STom Rini		};
611*1480fdf8STom Rini
612*1480fdf8STom Rini		vio_reg: regulator@1 {
613*1480fdf8STom Rini			regulator-always-on;
614*1480fdf8STom Rini		};
615*1480fdf8STom Rini
616*1480fdf8STom Rini		vdd1_reg: regulator@2 {
617*1480fdf8STom Rini			/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
618*1480fdf8STom Rini			regulator-name = "vdd_mpu";
619*1480fdf8STom Rini			regulator-min-microvolt = <912500>;
620*1480fdf8STom Rini			regulator-max-microvolt = <1312500>;
621*1480fdf8STom Rini			regulator-boot-on;
622*1480fdf8STom Rini			regulator-always-on;
623*1480fdf8STom Rini		};
624*1480fdf8STom Rini
625*1480fdf8STom Rini		vdd2_reg: regulator@3 {
626*1480fdf8STom Rini			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
627*1480fdf8STom Rini			regulator-name = "vdd_core";
628*1480fdf8STom Rini			regulator-min-microvolt = <912500>;
629*1480fdf8STom Rini			regulator-max-microvolt = <1150000>;
630*1480fdf8STom Rini			regulator-boot-on;
631*1480fdf8STom Rini			regulator-always-on;
632*1480fdf8STom Rini		};
633*1480fdf8STom Rini
634*1480fdf8STom Rini		vdd3_reg: regulator@4 {
635*1480fdf8STom Rini			regulator-always-on;
636*1480fdf8STom Rini		};
637*1480fdf8STom Rini
638*1480fdf8STom Rini		vdig1_reg: regulator@5 {
639*1480fdf8STom Rini			regulator-always-on;
640*1480fdf8STom Rini		};
641*1480fdf8STom Rini
642*1480fdf8STom Rini		vdig2_reg: regulator@6 {
643*1480fdf8STom Rini			regulator-always-on;
644*1480fdf8STom Rini		};
645*1480fdf8STom Rini
646*1480fdf8STom Rini		vpll_reg: regulator@7 {
647*1480fdf8STom Rini			regulator-always-on;
648*1480fdf8STom Rini		};
649*1480fdf8STom Rini
650*1480fdf8STom Rini		vdac_reg: regulator@8 {
651*1480fdf8STom Rini			regulator-always-on;
652*1480fdf8STom Rini		};
653*1480fdf8STom Rini
654*1480fdf8STom Rini		vaux1_reg: regulator@9 {
655*1480fdf8STom Rini			regulator-always-on;
656*1480fdf8STom Rini		};
657*1480fdf8STom Rini
658*1480fdf8STom Rini		vaux2_reg: regulator@10 {
659*1480fdf8STom Rini			regulator-always-on;
660*1480fdf8STom Rini		};
661*1480fdf8STom Rini
662*1480fdf8STom Rini		vaux33_reg: regulator@11 {
663*1480fdf8STom Rini			regulator-always-on;
664*1480fdf8STom Rini		};
665*1480fdf8STom Rini
666*1480fdf8STom Rini		vmmc_reg: regulator@12 {
667*1480fdf8STom Rini			regulator-min-microvolt = <1800000>;
668*1480fdf8STom Rini			regulator-max-microvolt = <3300000>;
669*1480fdf8STom Rini			regulator-always-on;
670*1480fdf8STom Rini		};
671*1480fdf8STom Rini	};
672*1480fdf8STom Rini};
673*1480fdf8STom Rini
674*1480fdf8STom Rini&mac {
675*1480fdf8STom Rini	pinctrl-names = "default", "sleep";
676*1480fdf8STom Rini	pinctrl-0 = <&cpsw_default>;
677*1480fdf8STom Rini	pinctrl-1 = <&cpsw_sleep>;
678*1480fdf8STom Rini	status = "okay";
679*1480fdf8STom Rini};
680*1480fdf8STom Rini
681*1480fdf8STom Rini&davinci_mdio {
682*1480fdf8STom Rini	pinctrl-names = "default", "sleep";
683*1480fdf8STom Rini	pinctrl-0 = <&davinci_mdio_default>;
684*1480fdf8STom Rini	pinctrl-1 = <&davinci_mdio_sleep>;
685*1480fdf8STom Rini	status = "okay";
686*1480fdf8STom Rini};
687*1480fdf8STom Rini
688*1480fdf8STom Rini&cpsw_emac0 {
689*1480fdf8STom Rini	phy_id = <&davinci_mdio>, <0>;
690*1480fdf8STom Rini	phy-mode = "rgmii-txid";
691*1480fdf8STom Rini};
692*1480fdf8STom Rini
693*1480fdf8STom Rini&cpsw_emac1 {
694*1480fdf8STom Rini	phy_id = <&davinci_mdio>, <1>;
695*1480fdf8STom Rini	phy-mode = "rgmii-txid";
696*1480fdf8STom Rini};
697*1480fdf8STom Rini
698*1480fdf8STom Rini&tscadc {
699*1480fdf8STom Rini	status = "okay";
700*1480fdf8STom Rini	tsc {
701*1480fdf8STom Rini		ti,wires = <4>;
702*1480fdf8STom Rini		ti,x-plate-resistance = <200>;
703*1480fdf8STom Rini		ti,coordinate-readouts = <5>;
704*1480fdf8STom Rini		ti,wire-config = <0x00 0x11 0x22 0x33>;
705*1480fdf8STom Rini		ti,charge-delay = <0x400>;
706*1480fdf8STom Rini	};
707*1480fdf8STom Rini
708*1480fdf8STom Rini	adc {
709*1480fdf8STom Rini		ti,adc-channels = <4 5 6 7>;
710*1480fdf8STom Rini	};
711*1480fdf8STom Rini};
712*1480fdf8STom Rini
713*1480fdf8STom Rini&mmc1 {
714*1480fdf8STom Rini	status = "okay";
715*1480fdf8STom Rini	vmmc-supply = <&vmmc_reg>;
716*1480fdf8STom Rini	bus-width = <4>;
717*1480fdf8STom Rini	pinctrl-names = "default";
718*1480fdf8STom Rini	pinctrl-0 = <&mmc1_pins>;
719*1480fdf8STom Rini	cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
720*1480fdf8STom Rini};
721*1480fdf8STom Rini
722*1480fdf8STom Rini&mmc3 {
723*1480fdf8STom Rini	/* these are on the crossbar and are outlined in the
724*1480fdf8STom Rini	   xbar-event-map element */
725*1480fdf8STom Rini	dmas = <&edma 12
726*1480fdf8STom Rini		&edma 13>;
727*1480fdf8STom Rini	dma-names = "tx", "rx";
728*1480fdf8STom Rini	status = "okay";
729*1480fdf8STom Rini	vmmc-supply = <&wlan_en_reg>;
730*1480fdf8STom Rini	bus-width = <4>;
731*1480fdf8STom Rini	pinctrl-names = "default";
732*1480fdf8STom Rini	pinctrl-0 = <&mmc3_pins &wlan_pins>;
733*1480fdf8STom Rini	ti,non-removable;
734*1480fdf8STom Rini	ti,needs-special-hs-handling;
735*1480fdf8STom Rini	cap-power-off-card;
736*1480fdf8STom Rini	keep-power-in-suspend;
737*1480fdf8STom Rini
738*1480fdf8STom Rini	#address-cells = <1>;
739*1480fdf8STom Rini	#size-cells = <0>;
740*1480fdf8STom Rini	wlcore: wlcore@0 {
741*1480fdf8STom Rini		compatible = "ti,wl1835";
742*1480fdf8STom Rini		reg = <2>;
743*1480fdf8STom Rini		interrupt-parent = <&gpio3>;
744*1480fdf8STom Rini		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
745*1480fdf8STom Rini	};
746*1480fdf8STom Rini};
747*1480fdf8STom Rini
748*1480fdf8STom Rini&edma {
749*1480fdf8STom Rini	ti,edma-xbar-event-map = /bits/ 16 <1 12
750*1480fdf8STom Rini					    2 13>;
751*1480fdf8STom Rini};
752*1480fdf8STom Rini
753*1480fdf8STom Rini&sham {
754*1480fdf8STom Rini	status = "okay";
755*1480fdf8STom Rini};
756*1480fdf8STom Rini
757*1480fdf8STom Rini&aes {
758*1480fdf8STom Rini	status = "okay";
759*1480fdf8STom Rini};
760*1480fdf8STom Rini
761*1480fdf8STom Rini&dcan1 {
762*1480fdf8STom Rini	status = "disabled";	/* Enable only if Profile 1 is selected */
763*1480fdf8STom Rini	pinctrl-names = "default";
764*1480fdf8STom Rini	pinctrl-0 = <&dcan1_pins_default>;
765*1480fdf8STom Rini};
766