1/* 2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * VScom OnRISC 11 * http://www.vscom.de 12 */ 13 14/dts-v1/; 15 16#include "am33xx.dtsi" 17#include <dt-bindings/pwm/pwm.h> 18 19/ { 20 model = "OnRISC Baltos"; 21 compatible = "vscom,onrisc", "ti,am33xx"; 22 23 chosen { 24 stdout-path = &uart0; 25 }; 26 27 cpus { 28 cpu@0 { 29 cpu0-supply = <&vdd1_reg>; 30 }; 31 }; 32 33 vbat: fixedregulator@0 { 34 compatible = "regulator-fixed"; 35 regulator-name = "vbat"; 36 regulator-min-microvolt = <5000000>; 37 regulator-max-microvolt = <5000000>; 38 regulator-boot-on; 39 }; 40}; 41 42&am33xx_pinmux { 43 mmc1_pins: pinmux_mmc1_pins { 44 pinctrl-single,pins = < 45 0xf0 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat3.mmc0_dat3 */ 46 0xf4 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat2.mmc0_dat2 */ 47 0xf8 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat1.mmc0_dat1 */ 48 0xfc (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_dat0.mmc0_dat0 */ 49 0x100 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_clk.mmc0_clk */ 50 0x104 (MUX_MODE0 | INPUT_EN | PULL_UP) /* mmc0_cmd.mmc0_cmd */ 51 >; 52 }; 53 54 i2c1_pins: pinmux_i2c1_pins { 55 pinctrl-single,pins = < 56 0x158 0x2a /* spi0_d1.i2c1_sda_mux3, INPUT | MODE2 */ 57 0x15c 0x2a /* spi0_cs0.i2c1_scl_mux3, INPUT | MODE2 */ 58 >; 59 }; 60 61 tps65910_pins: pinmux_tps65910_pins { 62 pinctrl-single,pins = < 63 0x078 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ 64 >; 65 66 }; 67 tca6416_pins: pinmux_tca6416_pins { 68 pinctrl-single,pins = < 69 AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ 70 >; 71 }; 72 73 uart0_pins: pinmux_uart0_pins { 74 pinctrl-single,pins = < 75 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 76 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 77 >; 78 }; 79 80 cpsw_default: cpsw_default { 81 pinctrl-single,pins = < 82 /* Slave 1 */ 83 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ 84 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ 85 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 86 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 87 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 88 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 89 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ 90 91 92 /* Slave 2 */ 93 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ 94 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ 95 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ 96 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ 97 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ 98 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ 99 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ 100 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ 101 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ 102 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ 103 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ 104 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ 105 >; 106 }; 107 108 cpsw_sleep: cpsw_sleep { 109 pinctrl-single,pins = < 110 /* Slave 1 reset value */ 111 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) 112 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 113 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 114 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 115 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 116 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 117 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) 118 119 /* Slave 2 reset value*/ 120 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) 121 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7) 122 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7) 123 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7) 124 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) 125 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) 126 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7) 127 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7) 128 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7) 129 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) 130 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) 131 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) 132 >; 133 }; 134 135 davinci_mdio_default: davinci_mdio_default { 136 pinctrl-single,pins = < 137 /* MDIO */ 138 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 139 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 140 >; 141 }; 142 143 davinci_mdio_sleep: davinci_mdio_sleep { 144 pinctrl-single,pins = < 145 /* MDIO reset value */ 146 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 147 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 148 >; 149 }; 150 151 nandflash_pins_s0: nandflash_pins_s0 { 152 pinctrl-single,pins = < 153 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 154 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 155 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 156 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 157 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 158 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 159 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 160 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 161 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 162 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 163 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 164 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 165 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 166 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 167 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 168 >; 169 }; 170}; 171 172&elm { 173 status = "okay"; 174}; 175 176&gpmc { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&nandflash_pins_s0>; 179 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ 180 status = "okay"; 181 182 nand@0,0 { 183 reg = <0 0 0>; /* CS0, offset 0 */ 184 nand-bus-width = <8>; 185 ti,nand-ecc-opt = "bch8"; 186 ti,nand-xfer-type = "polled"; 187 188 gpmc,device-nand = "true"; 189 gpmc,device-width = <1>; 190 gpmc,sync-clk-ps = <0>; 191 gpmc,cs-on-ns = <0>; 192 gpmc,cs-rd-off-ns = <44>; 193 gpmc,cs-wr-off-ns = <44>; 194 gpmc,adv-on-ns = <6>; 195 gpmc,adv-rd-off-ns = <34>; 196 gpmc,adv-wr-off-ns = <44>; 197 gpmc,we-on-ns = <0>; 198 gpmc,we-off-ns = <40>; 199 gpmc,oe-on-ns = <0>; 200 gpmc,oe-off-ns = <54>; 201 gpmc,access-ns = <64>; 202 gpmc,rd-cycle-ns = <82>; 203 gpmc,wr-cycle-ns = <82>; 204 gpmc,wait-on-read = "true"; 205 gpmc,wait-on-write = "true"; 206 gpmc,bus-turnaround-ns = <0>; 207 gpmc,cycle2cycle-delay-ns = <0>; 208 gpmc,clk-activation-ns = <0>; 209 gpmc,wait-monitoring-ns = <0>; 210 gpmc,wr-access-ns = <40>; 211 gpmc,wr-data-mux-bus-ns = <0>; 212 213 #address-cells = <1>; 214 #size-cells = <1>; 215 elm_id = <&elm>; 216 217 boot@0 { 218 label = "SPL"; 219 reg = <0x0 0x20000>; 220 }; 221 boot@20000{ 222 label = "SPL.backup1"; 223 reg = <0x20000 0x20000>; 224 }; 225 boot@40000 { 226 label = "SPL.backup2"; 227 reg = <0x40000 0x20000>; 228 }; 229 boot@60000 { 230 label = "SPL.backup3"; 231 reg = <0x60000 0x20000>; 232 }; 233 boot@80000 { 234 label = "u-boot"; 235 reg = <0x80000 0x1e0000>; 236 }; 237 boot@260000 { 238 label = "UBI"; 239 reg = <0x260000 0xfda0000>; 240 }; 241 }; 242}; 243 244&uart0 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&uart0_pins>; 247 248 status = "okay"; 249}; 250 251&i2c1 { 252 pinctrl-names = "default"; 253 pinctrl-0 = <&i2c1_pins>; 254 255 status = "okay"; 256 clock-frequency = <1000>; 257 258 tps: tps@2d { 259 reg = <0x2d>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 interrupt-parent = <&gpio1>; 263 interrupts = <28 GPIO_ACTIVE_LOW>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&tps65910_pins>; 266 }; 267 268 at24@50 { 269 compatible = "at24,24c02"; 270 pagesize = <8>; 271 reg = <0x50>; 272 }; 273 274 tca6416: gpio@20 { 275 compatible = "ti,tca6416"; 276 reg = <0x20>; 277 gpio-controller; 278 #gpio-cells = <2>; 279 interrupt-parent = <&gpio0>; 280 interrupts = <20 GPIO_ACTIVE_LOW>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&tca6416_pins>; 283 }; 284}; 285 286&usb { 287 status = "okay"; 288}; 289 290&usb_ctrl_mod { 291 status = "okay"; 292}; 293 294&usb0_phy { 295 status = "okay"; 296}; 297 298&usb1_phy { 299 status = "okay"; 300}; 301 302&usb0 { 303 status = "okay"; 304 dr_mode = "host"; 305}; 306 307&usb1 { 308 status = "okay"; 309 dr_mode = "host"; 310}; 311 312&cppi41dma { 313 status = "okay"; 314}; 315 316/include/ "tps65910.dtsi" 317 318&tps { 319 vcc1-supply = <&vbat>; 320 vcc2-supply = <&vbat>; 321 vcc3-supply = <&vbat>; 322 vcc4-supply = <&vbat>; 323 vcc5-supply = <&vbat>; 324 vcc6-supply = <&vbat>; 325 vcc7-supply = <&vbat>; 326 vccio-supply = <&vbat>; 327 328 ti,en-ck32k-xtal = <1>; 329 330 regulators { 331 vrtc_reg: regulator@0 { 332 regulator-always-on; 333 }; 334 335 vio_reg: regulator@1 { 336 regulator-always-on; 337 }; 338 339 vdd1_reg: regulator@2 { 340 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 341 regulator-name = "vdd_mpu"; 342 regulator-min-microvolt = <912500>; 343 regulator-max-microvolt = <1312500>; 344 regulator-boot-on; 345 regulator-always-on; 346 }; 347 348 vdd2_reg: regulator@3 { 349 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 350 regulator-name = "vdd_core"; 351 regulator-min-microvolt = <912500>; 352 regulator-max-microvolt = <1150000>; 353 regulator-boot-on; 354 regulator-always-on; 355 }; 356 357 vdd3_reg: regulator@4 { 358 regulator-always-on; 359 }; 360 361 vdig1_reg: regulator@5 { 362 regulator-always-on; 363 }; 364 365 vdig2_reg: regulator@6 { 366 regulator-always-on; 367 }; 368 369 vpll_reg: regulator@7 { 370 regulator-always-on; 371 }; 372 373 vdac_reg: regulator@8 { 374 regulator-always-on; 375 }; 376 377 vaux1_reg: regulator@9 { 378 regulator-always-on; 379 }; 380 381 vaux2_reg: regulator@10 { 382 regulator-always-on; 383 }; 384 385 vaux33_reg: regulator@11 { 386 regulator-always-on; 387 }; 388 389 vmmc_reg: regulator@12 { 390 regulator-min-microvolt = <1800000>; 391 regulator-max-microvolt = <3300000>; 392 regulator-always-on; 393 }; 394 }; 395}; 396 397&mac { 398 pinctrl-names = "default", "sleep"; 399 pinctrl-0 = <&cpsw_default>; 400 pinctrl-1 = <&cpsw_sleep>; 401 dual_emac = <1>; 402 403 status = "okay"; 404}; 405 406&davinci_mdio { 407 pinctrl-names = "default", "sleep"; 408 pinctrl-0 = <&davinci_mdio_default>; 409 pinctrl-1 = <&davinci_mdio_sleep>; 410 411 status = "okay"; 412}; 413 414&cpsw_emac0 { 415 phy_id = <&davinci_mdio>, <0>; 416 phy-mode = "rmii"; 417 dual_emac_res_vlan = <1>; 418}; 419 420&cpsw_emac1 { 421 phy_id = <&davinci_mdio>, <7>; 422 phy-mode = "rgmii-txid"; 423 dual_emac_res_vlan = <2>; 424}; 425 426&phy_sel { 427 rmii-clock-ext = <1>; 428}; 429 430&mmc1 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&mmc1_pins>; 433 vmmc-supply = <&vmmc_reg>; 434 status = "okay"; 435}; 436 437&gpio0 { 438 ti,no-reset-on-init; 439}; 440