1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * armboot - Startup Code for SA1100 CPU 4 * 5 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 6 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 7 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 8 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 9 */ 10 11 #include <asm-offsets.h> 12 #include <config.h> 13 14 /* 15 ************************************************************************* 16 * 17 * Startup Code (reset vector) 18 * 19 * do important init only if we don't start from memory! 20 * relocate armboot to ram 21 * setup stack 22 * jump to second stage 23 * 24 ************************************************************************* 25 */ 26 27 .globl reset 28 29 reset: 30 /* 31 * set the cpu to SVC32 mode 32 */ 33 mrs r0,cpsr 34 bic r0,r0,#0x1f 35 orr r0,r0,#0xd3 36 msr cpsr,r0 37 38 /* 39 * we do sys-critical inits only at reboot, 40 * not when booting from ram! 41 */ 42 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 43 bl cpu_init_crit 44 #endif 45 46 bl _main 47 48 /*------------------------------------------------------------------------------*/ 49 50 .globl c_runtime_cpu_setup 51 c_runtime_cpu_setup: 52 53 mov pc, lr 54 55 /* 56 ************************************************************************* 57 * 58 * CPU_init_critical registers 59 * 60 * setup important registers 61 * setup memory timing 62 * 63 ************************************************************************* 64 */ 65 66 67 /* Interrupt-Controller base address */ 68 IC_BASE: .word 0x90050000 69 #define ICMR 0x04 70 71 72 /* Reset-Controller */ 73 RST_BASE: .word 0x90030000 74 #define RSRR 0x00 75 #define RCSR 0x04 76 77 78 /* PWR */ 79 PWR_BASE: .word 0x90020000 80 #define PSPR 0x08 81 #define PPCR 0x14 82 cpuspeed: .word CONFIG_SYS_CPUSPEED 83 84 85 cpu_init_crit: 86 /* 87 * mask all IRQs 88 */ 89 ldr r0, IC_BASE 90 mov r1, #0x00 91 str r1, [r0, #ICMR] 92 93 /* set clock speed */ 94 ldr r0, PWR_BASE 95 ldr r1, cpuspeed 96 str r1, [r0, #PPCR] 97 98 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY 99 /* 100 * before relocating, we have to setup RAM timing 101 * because memory timing is board-dependend, you will 102 * find a lowlevel_init.S in your board directory. 103 */ 104 mov ip, lr 105 bl lowlevel_init 106 mov lr, ip 107 #endif 108 109 /* 110 * disable MMU stuff and enable I-cache 111 */ 112 mrc p15,0,r0,c1,c0 113 bic r0, r0, #0x00002000 @ clear bit 13 (X) 114 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 115 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 116 orr r0, r0, #0x00000002 @ set bit 1 (A) Align 117 mcr p15,0,r0,c1,c0 118 119 /* 120 * flush v4 I/D caches 121 */ 122 mov r0, #0 123 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 124 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 125 126 mov pc, lr 127