1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12#include <asm-offsets.h> 13#include <config.h> 14#include <version.h> 15 16/* 17 ************************************************************************* 18 * 19 * Startup Code (reset vector) 20 * 21 * do important init only if we don't start from memory! 22 * relocate armboot to ram 23 * setup stack 24 * jump to second stage 25 * 26 ************************************************************************* 27 */ 28 29 .globl reset 30 31reset: 32 /* 33 * set the cpu to SVC32 mode 34 */ 35 mrs r0,cpsr 36 bic r0,r0,#0x1f 37 orr r0,r0,#0xd3 38 msr cpsr,r0 39 40 /* 41 * we do sys-critical inits only at reboot, 42 * not when booting from ram! 43 */ 44#ifndef CONFIG_SKIP_LOWLEVEL_INIT 45 bl cpu_init_crit 46#endif 47 48 bl _main 49 50/*------------------------------------------------------------------------------*/ 51 52 .globl c_runtime_cpu_setup 53c_runtime_cpu_setup: 54 55 mov pc, lr 56 57/* 58 ************************************************************************* 59 * 60 * CPU_init_critical registers 61 * 62 * setup important registers 63 * setup memory timing 64 * 65 ************************************************************************* 66 */ 67 68 69/* Interrupt-Controller base address */ 70IC_BASE: .word 0x90050000 71#define ICMR 0x04 72 73 74/* Reset-Controller */ 75RST_BASE: .word 0x90030000 76#define RSRR 0x00 77#define RCSR 0x04 78 79 80/* PWR */ 81PWR_BASE: .word 0x90020000 82#define PSPR 0x08 83#define PPCR 0x14 84cpuspeed: .word CONFIG_SYS_CPUSPEED 85 86 87cpu_init_crit: 88 /* 89 * mask all IRQs 90 */ 91 ldr r0, IC_BASE 92 mov r1, #0x00 93 str r1, [r0, #ICMR] 94 95 /* set clock speed */ 96 ldr r0, PWR_BASE 97 ldr r1, cpuspeed 98 str r1, [r0, #PPCR] 99 100 /* 101 * before relocating, we have to setup RAM timing 102 * because memory timing is board-dependend, you will 103 * find a lowlevel_init.S in your board directory. 104 */ 105 mov ip, lr 106 bl lowlevel_init 107 mov lr, ip 108 109 /* 110 * disable MMU stuff and enable I-cache 111 */ 112 mrc p15,0,r0,c1,c0 113 bic r0, r0, #0x00002000 @ clear bit 13 (X) 114 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 115 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 116 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 117 mcr p15,0,r0,c1,c0 118 119 /* 120 * flush v4 I/D caches 121 */ 122 mov r0, #0 123 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 124 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 125 126 mov pc, lr 127