1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77 .word CONFIG_SYS_TEXT_BASE 78 79/* 80 * These are defined in the board-specific linker script. 81 * Subtracting _start from them lets the linker put their 82 * relative position in the executable instead of leaving 83 * them null. 84 */ 85.globl _bss_start_ofs 86_bss_start_ofs: 87 .word __bss_start - _start 88 89.globl _bss_end_ofs 90_bss_end_ofs: 91 .word __bss_end__ - _start 92 93.globl _end_ofs 94_end_ofs: 95 .word _end - _start 96 97#ifdef CONFIG_USE_IRQ 98/* IRQ stack memory (calculated at run-time) */ 99.globl IRQ_STACK_START 100IRQ_STACK_START: 101 .word 0x0badc0de 102 103/* IRQ stack memory (calculated at run-time) */ 104.globl FIQ_STACK_START 105FIQ_STACK_START: 106 .word 0x0badc0de 107#endif 108 109/* IRQ stack memory (calculated at run-time) + 8 bytes */ 110.globl IRQ_STACK_START_IN 111IRQ_STACK_START_IN: 112 .word 0x0badc0de 113 114/* 115 * the actual reset code 116 */ 117 118reset: 119 /* 120 * set the cpu to SVC32 mode 121 */ 122 mrs r0,cpsr 123 bic r0,r0,#0x1f 124 orr r0,r0,#0xd3 125 msr cpsr,r0 126 127 /* 128 * we do sys-critical inits only at reboot, 129 * not when booting from ram! 130 */ 131#ifndef CONFIG_SKIP_LOWLEVEL_INIT 132 bl cpu_init_crit 133#endif 134 135/* Set stackpointer in internal RAM to call board_init_f */ 136call_board_init_f: 137 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 138 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 139 ldr r0,=0x00000000 140 bl board_init_f 141 142/*------------------------------------------------------------------------------*/ 143 144/* 145 * void relocate_code (addr_sp, gd, addr_moni) 146 * 147 * This "function" does not return, instead it continues in RAM 148 * after relocating the monitor code. 149 * 150 */ 151 .globl relocate_code 152relocate_code: 153 mov r4, r0 /* save addr_sp */ 154 mov r5, r1 /* save addr of gd */ 155 mov r6, r2 /* save addr of destination */ 156 157 /* Set up the stack */ 158stack_setup: 159 mov sp, r4 160 161 adr r0, _start 162 cmp r0, r6 163 beq clear_bss /* skip relocation */ 164 mov r1, r6 /* r1 <- scratch for copy_loop */ 165 ldr r3, _bss_start_ofs 166 add r2, r0, r3 /* r2 <- source end address */ 167 168copy_loop: 169 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 170 stmia r1!, {r9-r10} /* copy to target address [r1] */ 171 cmp r0, r2 /* until source end address [r2] */ 172 blo copy_loop 173 174#ifndef CONFIG_SPL_BUILD 175 /* 176 * fix .rel.dyn relocations 177 */ 178 ldr r0, _TEXT_BASE /* r0 <- Text base */ 179 sub r9, r6, r0 /* r9 <- relocation offset */ 180 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 181 add r10, r10, r0 /* r10 <- sym table in FLASH */ 182 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 183 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 184 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 185 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 186fixloop: 187 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 188 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 189 ldr r1, [r2, #4] 190 and r7, r1, #0xff 191 cmp r7, #23 /* relative fixup? */ 192 beq fixrel 193 cmp r7, #2 /* absolute fixup? */ 194 beq fixabs 195 /* ignore unknown type of fixup */ 196 b fixnext 197fixabs: 198 /* absolute fix: set location to (offset) symbol value */ 199 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 200 add r1, r10, r1 /* r1 <- address of symbol in table */ 201 ldr r1, [r1, #4] /* r1 <- symbol value */ 202 add r1, r1, r9 /* r1 <- relocated sym addr */ 203 b fixnext 204fixrel: 205 /* relative fix: increase location by offset */ 206 ldr r1, [r0] 207 add r1, r1, r9 208fixnext: 209 str r1, [r0] 210 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 211 cmp r2, r3 212 blo fixloop 213#endif 214 215clear_bss: 216#ifndef CONFIG_SPL_BUILD 217 ldr r0, _bss_start_ofs 218 ldr r1, _bss_end_ofs 219 mov r4, r6 /* reloc addr */ 220 add r0, r0, r4 221 add r1, r1, r4 222 mov r2, #0x00000000 /* clear */ 223 224clbss_l:str r2, [r0] /* clear loop... */ 225 add r0, r0, #4 226 cmp r0, r1 227 bne clbss_l 228#endif 229 230/* 231 * We are done. Do not return, instead branch to second part of board 232 * initialization, now running from RAM. 233 */ 234 ldr r0, _board_init_r_ofs 235 adr r1, _start 236 add lr, r0, r1 237 add lr, lr, r9 238 /* setup parameters for board_init_r */ 239 mov r0, r5 /* gd_t */ 240 mov r1, r6 /* dest_addr */ 241 /* jump to it ... */ 242 mov pc, lr 243 244_board_init_r_ofs: 245 .word board_init_r - _start 246 247_rel_dyn_start_ofs: 248 .word __rel_dyn_start - _start 249_rel_dyn_end_ofs: 250 .word __rel_dyn_end - _start 251_dynsym_start_ofs: 252 .word __dynsym_start - _start 253 254/* 255 ************************************************************************* 256 * 257 * CPU_init_critical registers 258 * 259 * setup important registers 260 * setup memory timing 261 * 262 ************************************************************************* 263 */ 264 265 266/* Interrupt-Controller base address */ 267IC_BASE: .word 0x90050000 268#define ICMR 0x04 269 270 271/* Reset-Controller */ 272RST_BASE: .word 0x90030000 273#define RSRR 0x00 274#define RCSR 0x04 275 276 277/* PWR */ 278PWR_BASE: .word 0x90020000 279#define PSPR 0x08 280#define PPCR 0x14 281cpuspeed: .word CONFIG_SYS_CPUSPEED 282 283 284cpu_init_crit: 285 /* 286 * mask all IRQs 287 */ 288 ldr r0, IC_BASE 289 mov r1, #0x00 290 str r1, [r0, #ICMR] 291 292 /* set clock speed */ 293 ldr r0, PWR_BASE 294 ldr r1, cpuspeed 295 str r1, [r0, #PPCR] 296 297 /* 298 * before relocating, we have to setup RAM timing 299 * because memory timing is board-dependend, you will 300 * find a lowlevel_init.S in your board directory. 301 */ 302 mov ip, lr 303 bl lowlevel_init 304 mov lr, ip 305 306 /* 307 * disable MMU stuff and enable I-cache 308 */ 309 mrc p15,0,r0,c1,c0 310 bic r0, r0, #0x00002000 @ clear bit 13 (X) 311 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 312 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 313 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 314 mcr p15,0,r0,c1,c0 315 316 /* 317 * flush v4 I/D caches 318 */ 319 mov r0, #0 320 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 321 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 322 323 mov pc, lr 324 325 326/* 327 ************************************************************************* 328 * 329 * Interrupt handling 330 * 331 ************************************************************************* 332 */ 333 334@ 335@ IRQ stack frame. 336@ 337#define S_FRAME_SIZE 72 338 339#define S_OLD_R0 68 340#define S_PSR 64 341#define S_PC 60 342#define S_LR 56 343#define S_SP 52 344 345#define S_IP 48 346#define S_FP 44 347#define S_R10 40 348#define S_R9 36 349#define S_R8 32 350#define S_R7 28 351#define S_R6 24 352#define S_R5 20 353#define S_R4 16 354#define S_R3 12 355#define S_R2 8 356#define S_R1 4 357#define S_R0 0 358 359#define MODE_SVC 0x13 360#define I_BIT 0x80 361 362/* 363 * use bad_save_user_regs for abort/prefetch/undef/swi ... 364 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 365 */ 366 367 .macro bad_save_user_regs 368 sub sp, sp, #S_FRAME_SIZE 369 stmia sp, {r0 - r12} @ Calling r0-r12 370 add r8, sp, #S_PC 371 372 ldr r2, IRQ_STACK_START_IN 373 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 374 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 375 376 add r5, sp, #S_SP 377 mov r1, lr 378 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 379 mov r0, sp 380 .endm 381 382 .macro irq_save_user_regs 383 sub sp, sp, #S_FRAME_SIZE 384 stmia sp, {r0 - r12} @ Calling r0-r12 385 add r8, sp, #S_PC 386 stmdb r8, {sp, lr}^ @ Calling SP, LR 387 str lr, [r8, #0] @ Save calling PC 388 mrs r6, spsr 389 str r6, [r8, #4] @ Save CPSR 390 str r0, [r8, #8] @ Save OLD_R0 391 mov r0, sp 392 .endm 393 394 .macro irq_restore_user_regs 395 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 396 mov r0, r0 397 ldr lr, [sp, #S_PC] @ Get PC 398 add sp, sp, #S_FRAME_SIZE 399 subs pc, lr, #4 @ return & move spsr_svc into cpsr 400 .endm 401 402 .macro get_bad_stack 403 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 404 405 str lr, [r13] @ save caller lr / spsr 406 mrs lr, spsr 407 str lr, [r13, #4] 408 409 mov r13, #MODE_SVC @ prepare SVC-Mode 410 msr spsr_c, r13 411 mov lr, pc 412 movs pc, lr 413 .endm 414 415 .macro get_irq_stack @ setup IRQ stack 416 ldr sp, IRQ_STACK_START 417 .endm 418 419 .macro get_fiq_stack @ setup FIQ stack 420 ldr sp, FIQ_STACK_START 421 .endm 422 423/* 424 * exception handlers 425 */ 426 .align 5 427undefined_instruction: 428 get_bad_stack 429 bad_save_user_regs 430 bl do_undefined_instruction 431 432 .align 5 433software_interrupt: 434 get_bad_stack 435 bad_save_user_regs 436 bl do_software_interrupt 437 438 .align 5 439prefetch_abort: 440 get_bad_stack 441 bad_save_user_regs 442 bl do_prefetch_abort 443 444 .align 5 445data_abort: 446 get_bad_stack 447 bad_save_user_regs 448 bl do_data_abort 449 450 .align 5 451not_used: 452 get_bad_stack 453 bad_save_user_regs 454 bl do_not_used 455 456#ifdef CONFIG_USE_IRQ 457 458 .align 5 459irq: 460 get_irq_stack 461 irq_save_user_regs 462 bl do_irq 463 irq_restore_user_regs 464 465 .align 5 466fiq: 467 get_fiq_stack 468 /* someone ought to write a more effiction fiq_save_user_regs */ 469 irq_save_user_regs 470 bl do_fiq 471 irq_restore_user_regs 472 473#else 474 475 .align 5 476irq: 477 get_bad_stack 478 bad_save_user_regs 479 bl do_irq 480 481 .align 5 482fiq: 483 get_bad_stack 484 bad_save_user_regs 485 bl do_fiq 486 487#endif 488 489 .align 5 490.globl reset_cpu 491reset_cpu: 492 ldr r0, RST_BASE 493 mov r1, #0x0 @ set bit 3-0 ... 494 str r1, [r0, #RCSR] @ ... to clear in RCSR 495 mov r1, #0x1 496 str r1, [r0, #RSRR] @ and perform reset 497 b reset_cpu @ silly, but repeat endlessly 498