1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) 78 .word CONFIG_SPL_TEXT_BASE 79#else 80 .word CONFIG_SYS_TEXT_BASE 81#endif 82 83/* 84 * These are defined in the board-specific linker script. 85 * Subtracting _start from them lets the linker put their 86 * relative position in the executable instead of leaving 87 * them null. 88 */ 89.globl _bss_start_ofs 90_bss_start_ofs: 91 .word __bss_start - _start 92 93.globl _bss_end_ofs 94_bss_end_ofs: 95 .word __bss_end - _start 96 97.globl _end_ofs 98_end_ofs: 99 .word _end - _start 100 101#ifdef CONFIG_USE_IRQ 102/* IRQ stack memory (calculated at run-time) */ 103.globl IRQ_STACK_START 104IRQ_STACK_START: 105 .word 0x0badc0de 106 107/* IRQ stack memory (calculated at run-time) */ 108.globl FIQ_STACK_START 109FIQ_STACK_START: 110 .word 0x0badc0de 111#endif 112 113/* IRQ stack memory (calculated at run-time) + 8 bytes */ 114.globl IRQ_STACK_START_IN 115IRQ_STACK_START_IN: 116 .word 0x0badc0de 117 118/* 119 * the actual reset code 120 */ 121 122reset: 123 /* 124 * set the cpu to SVC32 mode 125 */ 126 mrs r0,cpsr 127 bic r0,r0,#0x1f 128 orr r0,r0,#0xd3 129 msr cpsr,r0 130 131 /* 132 * we do sys-critical inits only at reboot, 133 * not when booting from ram! 134 */ 135#ifndef CONFIG_SKIP_LOWLEVEL_INIT 136 bl cpu_init_crit 137#endif 138 139 bl _main 140 141/*------------------------------------------------------------------------------*/ 142 143 .globl c_runtime_cpu_setup 144c_runtime_cpu_setup: 145 146 mov pc, lr 147 148/* 149 ************************************************************************* 150 * 151 * CPU_init_critical registers 152 * 153 * setup important registers 154 * setup memory timing 155 * 156 ************************************************************************* 157 */ 158 159 160/* Interrupt-Controller base address */ 161IC_BASE: .word 0x90050000 162#define ICMR 0x04 163 164 165/* Reset-Controller */ 166RST_BASE: .word 0x90030000 167#define RSRR 0x00 168#define RCSR 0x04 169 170 171/* PWR */ 172PWR_BASE: .word 0x90020000 173#define PSPR 0x08 174#define PPCR 0x14 175cpuspeed: .word CONFIG_SYS_CPUSPEED 176 177 178cpu_init_crit: 179 /* 180 * mask all IRQs 181 */ 182 ldr r0, IC_BASE 183 mov r1, #0x00 184 str r1, [r0, #ICMR] 185 186 /* set clock speed */ 187 ldr r0, PWR_BASE 188 ldr r1, cpuspeed 189 str r1, [r0, #PPCR] 190 191 /* 192 * before relocating, we have to setup RAM timing 193 * because memory timing is board-dependend, you will 194 * find a lowlevel_init.S in your board directory. 195 */ 196 mov ip, lr 197 bl lowlevel_init 198 mov lr, ip 199 200 /* 201 * disable MMU stuff and enable I-cache 202 */ 203 mrc p15,0,r0,c1,c0 204 bic r0, r0, #0x00002000 @ clear bit 13 (X) 205 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 206 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 207 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 208 mcr p15,0,r0,c1,c0 209 210 /* 211 * flush v4 I/D caches 212 */ 213 mov r0, #0 214 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 215 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 216 217 mov pc, lr 218 219 220/* 221 ************************************************************************* 222 * 223 * Interrupt handling 224 * 225 ************************************************************************* 226 */ 227 228@ 229@ IRQ stack frame. 230@ 231#define S_FRAME_SIZE 72 232 233#define S_OLD_R0 68 234#define S_PSR 64 235#define S_PC 60 236#define S_LR 56 237#define S_SP 52 238 239#define S_IP 48 240#define S_FP 44 241#define S_R10 40 242#define S_R9 36 243#define S_R8 32 244#define S_R7 28 245#define S_R6 24 246#define S_R5 20 247#define S_R4 16 248#define S_R3 12 249#define S_R2 8 250#define S_R1 4 251#define S_R0 0 252 253#define MODE_SVC 0x13 254#define I_BIT 0x80 255 256/* 257 * use bad_save_user_regs for abort/prefetch/undef/swi ... 258 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 259 */ 260 261 .macro bad_save_user_regs 262 sub sp, sp, #S_FRAME_SIZE 263 stmia sp, {r0 - r12} @ Calling r0-r12 264 add r8, sp, #S_PC 265 266 ldr r2, IRQ_STACK_START_IN 267 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 268 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 269 270 add r5, sp, #S_SP 271 mov r1, lr 272 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 273 mov r0, sp 274 .endm 275 276 .macro irq_save_user_regs 277 sub sp, sp, #S_FRAME_SIZE 278 stmia sp, {r0 - r12} @ Calling r0-r12 279 add r8, sp, #S_PC 280 stmdb r8, {sp, lr}^ @ Calling SP, LR 281 str lr, [r8, #0] @ Save calling PC 282 mrs r6, spsr 283 str r6, [r8, #4] @ Save CPSR 284 str r0, [r8, #8] @ Save OLD_R0 285 mov r0, sp 286 .endm 287 288 .macro irq_restore_user_regs 289 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 290 mov r0, r0 291 ldr lr, [sp, #S_PC] @ Get PC 292 add sp, sp, #S_FRAME_SIZE 293 subs pc, lr, #4 @ return & move spsr_svc into cpsr 294 .endm 295 296 .macro get_bad_stack 297 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 298 299 str lr, [r13] @ save caller lr / spsr 300 mrs lr, spsr 301 str lr, [r13, #4] 302 303 mov r13, #MODE_SVC @ prepare SVC-Mode 304 msr spsr_c, r13 305 mov lr, pc 306 movs pc, lr 307 .endm 308 309 .macro get_irq_stack @ setup IRQ stack 310 ldr sp, IRQ_STACK_START 311 .endm 312 313 .macro get_fiq_stack @ setup FIQ stack 314 ldr sp, FIQ_STACK_START 315 .endm 316 317/* 318 * exception handlers 319 */ 320 .align 5 321undefined_instruction: 322 get_bad_stack 323 bad_save_user_regs 324 bl do_undefined_instruction 325 326 .align 5 327software_interrupt: 328 get_bad_stack 329 bad_save_user_regs 330 bl do_software_interrupt 331 332 .align 5 333prefetch_abort: 334 get_bad_stack 335 bad_save_user_regs 336 bl do_prefetch_abort 337 338 .align 5 339data_abort: 340 get_bad_stack 341 bad_save_user_regs 342 bl do_data_abort 343 344 .align 5 345not_used: 346 get_bad_stack 347 bad_save_user_regs 348 bl do_not_used 349 350#ifdef CONFIG_USE_IRQ 351 352 .align 5 353irq: 354 get_irq_stack 355 irq_save_user_regs 356 bl do_irq 357 irq_restore_user_regs 358 359 .align 5 360fiq: 361 get_fiq_stack 362 /* someone ought to write a more effiction fiq_save_user_regs */ 363 irq_save_user_regs 364 bl do_fiq 365 irq_restore_user_regs 366 367#else 368 369 .align 5 370irq: 371 get_bad_stack 372 bad_save_user_regs 373 bl do_irq 374 375 .align 5 376fiq: 377 get_bad_stack 378 bad_save_user_regs 379 bl do_fiq 380 381#endif 382 383 .align 5 384.globl reset_cpu 385reset_cpu: 386 ldr r0, RST_BASE 387 mov r1, #0x0 @ set bit 3-0 ... 388 str r1, [r0, #RCSR] @ ... to clear in RCSR 389 mov r1, #0x1 390 str r1, [r0, #RSRR] @ and perform reset 391 b reset_cpu @ silly, but repeat endlessly 392