1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77 .word CONFIG_SYS_TEXT_BASE 78 79/* 80 * These are defined in the board-specific linker script. 81 * Subtracting _start from them lets the linker put their 82 * relative position in the executable instead of leaving 83 * them null. 84 */ 85.globl _bss_start_ofs 86_bss_start_ofs: 87 .word __bss_start - _start 88 89.globl _bss_end_ofs 90_bss_end_ofs: 91 .word __bss_end__ - _start 92 93.globl _end_ofs 94_end_ofs: 95 .word _end - _start 96 97#ifdef CONFIG_USE_IRQ 98/* IRQ stack memory (calculated at run-time) */ 99.globl IRQ_STACK_START 100IRQ_STACK_START: 101 .word 0x0badc0de 102 103/* IRQ stack memory (calculated at run-time) */ 104.globl FIQ_STACK_START 105FIQ_STACK_START: 106 .word 0x0badc0de 107#endif 108 109/* IRQ stack memory (calculated at run-time) + 8 bytes */ 110.globl IRQ_STACK_START_IN 111IRQ_STACK_START_IN: 112 .word 0x0badc0de 113 114/* 115 * the actual reset code 116 */ 117 118reset: 119 /* 120 * set the cpu to SVC32 mode 121 */ 122 mrs r0,cpsr 123 bic r0,r0,#0x1f 124 orr r0,r0,#0xd3 125 msr cpsr,r0 126 127 /* 128 * we do sys-critical inits only at reboot, 129 * not when booting from ram! 130 */ 131#ifndef CONFIG_SKIP_LOWLEVEL_INIT 132 bl cpu_init_crit 133#endif 134 135/* Set stackpointer in internal RAM to call board_init_f */ 136call_board_init_f: 137 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 138 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 139 ldr r0,=0x00000000 140 bl board_init_f 141 142/*------------------------------------------------------------------------------*/ 143 144/* 145 * void relocate_code (addr_sp, gd, addr_moni) 146 * 147 * This "function" does not return, instead it continues in RAM 148 * after relocating the monitor code. 149 * 150 */ 151 .globl relocate_code 152relocate_code: 153 mov r4, r0 /* save addr_sp */ 154 mov r5, r1 /* save addr of gd */ 155 mov r6, r2 /* save addr of destination */ 156 157 /* Set up the stack */ 158stack_setup: 159 mov sp, r4 160 161 adr r0, _start 162 cmp r0, r6 163 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 164 beq clear_bss /* skip relocation */ 165 mov r1, r6 /* r1 <- scratch for copy_loop */ 166 ldr r3, _bss_start_ofs 167 add r2, r0, r3 /* r2 <- source end address */ 168 169copy_loop: 170 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 171 stmia r1!, {r9-r10} /* copy to target address [r1] */ 172 cmp r0, r2 /* until source end address [r2] */ 173 blo copy_loop 174 175#ifndef CONFIG_SPL_BUILD 176 /* 177 * fix .rel.dyn relocations 178 */ 179 ldr r0, _TEXT_BASE /* r0 <- Text base */ 180 sub r9, r6, r0 /* r9 <- relocation offset */ 181 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 182 add r10, r10, r0 /* r10 <- sym table in FLASH */ 183 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 184 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 185 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 186 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 187fixloop: 188 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 189 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 190 ldr r1, [r2, #4] 191 and r7, r1, #0xff 192 cmp r7, #23 /* relative fixup? */ 193 beq fixrel 194 cmp r7, #2 /* absolute fixup? */ 195 beq fixabs 196 /* ignore unknown type of fixup */ 197 b fixnext 198fixabs: 199 /* absolute fix: set location to (offset) symbol value */ 200 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 201 add r1, r10, r1 /* r1 <- address of symbol in table */ 202 ldr r1, [r1, #4] /* r1 <- symbol value */ 203 add r1, r1, r9 /* r1 <- relocated sym addr */ 204 b fixnext 205fixrel: 206 /* relative fix: increase location by offset */ 207 ldr r1, [r0] 208 add r1, r1, r9 209fixnext: 210 str r1, [r0] 211 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 212 cmp r2, r3 213 blo fixloop 214#endif 215 216clear_bss: 217#ifndef CONFIG_SPL_BUILD 218 ldr r0, _bss_start_ofs 219 ldr r1, _bss_end_ofs 220 mov r4, r6 /* reloc addr */ 221 add r0, r0, r4 222 add r1, r1, r4 223 mov r2, #0x00000000 /* clear */ 224 225clbss_l:cmp r0, r1 /* clear loop... */ 226 bhs clbss_e /* if reached end of bss, exit */ 227 str r2, [r0] 228 add r0, r0, #4 229 b clbss_l 230clbss_e: 231#endif 232 233/* 234 * We are done. Do not return, instead branch to second part of board 235 * initialization, now running from RAM. 236 */ 237 ldr r0, _board_init_r_ofs 238 adr r1, _start 239 add lr, r0, r1 240 add lr, lr, r9 241 /* setup parameters for board_init_r */ 242 mov r0, r5 /* gd_t */ 243 mov r1, r6 /* dest_addr */ 244 /* jump to it ... */ 245 mov pc, lr 246 247_board_init_r_ofs: 248 .word board_init_r - _start 249 250_rel_dyn_start_ofs: 251 .word __rel_dyn_start - _start 252_rel_dyn_end_ofs: 253 .word __rel_dyn_end - _start 254_dynsym_start_ofs: 255 .word __dynsym_start - _start 256 257/* 258 ************************************************************************* 259 * 260 * CPU_init_critical registers 261 * 262 * setup important registers 263 * setup memory timing 264 * 265 ************************************************************************* 266 */ 267 268 269/* Interrupt-Controller base address */ 270IC_BASE: .word 0x90050000 271#define ICMR 0x04 272 273 274/* Reset-Controller */ 275RST_BASE: .word 0x90030000 276#define RSRR 0x00 277#define RCSR 0x04 278 279 280/* PWR */ 281PWR_BASE: .word 0x90020000 282#define PSPR 0x08 283#define PPCR 0x14 284cpuspeed: .word CONFIG_SYS_CPUSPEED 285 286 287cpu_init_crit: 288 /* 289 * mask all IRQs 290 */ 291 ldr r0, IC_BASE 292 mov r1, #0x00 293 str r1, [r0, #ICMR] 294 295 /* set clock speed */ 296 ldr r0, PWR_BASE 297 ldr r1, cpuspeed 298 str r1, [r0, #PPCR] 299 300 /* 301 * before relocating, we have to setup RAM timing 302 * because memory timing is board-dependend, you will 303 * find a lowlevel_init.S in your board directory. 304 */ 305 mov ip, lr 306 bl lowlevel_init 307 mov lr, ip 308 309 /* 310 * disable MMU stuff and enable I-cache 311 */ 312 mrc p15,0,r0,c1,c0 313 bic r0, r0, #0x00002000 @ clear bit 13 (X) 314 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 315 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 316 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 317 mcr p15,0,r0,c1,c0 318 319 /* 320 * flush v4 I/D caches 321 */ 322 mov r0, #0 323 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 324 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 325 326 mov pc, lr 327 328 329/* 330 ************************************************************************* 331 * 332 * Interrupt handling 333 * 334 ************************************************************************* 335 */ 336 337@ 338@ IRQ stack frame. 339@ 340#define S_FRAME_SIZE 72 341 342#define S_OLD_R0 68 343#define S_PSR 64 344#define S_PC 60 345#define S_LR 56 346#define S_SP 52 347 348#define S_IP 48 349#define S_FP 44 350#define S_R10 40 351#define S_R9 36 352#define S_R8 32 353#define S_R7 28 354#define S_R6 24 355#define S_R5 20 356#define S_R4 16 357#define S_R3 12 358#define S_R2 8 359#define S_R1 4 360#define S_R0 0 361 362#define MODE_SVC 0x13 363#define I_BIT 0x80 364 365/* 366 * use bad_save_user_regs for abort/prefetch/undef/swi ... 367 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 368 */ 369 370 .macro bad_save_user_regs 371 sub sp, sp, #S_FRAME_SIZE 372 stmia sp, {r0 - r12} @ Calling r0-r12 373 add r8, sp, #S_PC 374 375 ldr r2, IRQ_STACK_START_IN 376 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 377 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 378 379 add r5, sp, #S_SP 380 mov r1, lr 381 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 382 mov r0, sp 383 .endm 384 385 .macro irq_save_user_regs 386 sub sp, sp, #S_FRAME_SIZE 387 stmia sp, {r0 - r12} @ Calling r0-r12 388 add r8, sp, #S_PC 389 stmdb r8, {sp, lr}^ @ Calling SP, LR 390 str lr, [r8, #0] @ Save calling PC 391 mrs r6, spsr 392 str r6, [r8, #4] @ Save CPSR 393 str r0, [r8, #8] @ Save OLD_R0 394 mov r0, sp 395 .endm 396 397 .macro irq_restore_user_regs 398 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 399 mov r0, r0 400 ldr lr, [sp, #S_PC] @ Get PC 401 add sp, sp, #S_FRAME_SIZE 402 subs pc, lr, #4 @ return & move spsr_svc into cpsr 403 .endm 404 405 .macro get_bad_stack 406 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 407 408 str lr, [r13] @ save caller lr / spsr 409 mrs lr, spsr 410 str lr, [r13, #4] 411 412 mov r13, #MODE_SVC @ prepare SVC-Mode 413 msr spsr_c, r13 414 mov lr, pc 415 movs pc, lr 416 .endm 417 418 .macro get_irq_stack @ setup IRQ stack 419 ldr sp, IRQ_STACK_START 420 .endm 421 422 .macro get_fiq_stack @ setup FIQ stack 423 ldr sp, FIQ_STACK_START 424 .endm 425 426/* 427 * exception handlers 428 */ 429 .align 5 430undefined_instruction: 431 get_bad_stack 432 bad_save_user_regs 433 bl do_undefined_instruction 434 435 .align 5 436software_interrupt: 437 get_bad_stack 438 bad_save_user_regs 439 bl do_software_interrupt 440 441 .align 5 442prefetch_abort: 443 get_bad_stack 444 bad_save_user_regs 445 bl do_prefetch_abort 446 447 .align 5 448data_abort: 449 get_bad_stack 450 bad_save_user_regs 451 bl do_data_abort 452 453 .align 5 454not_used: 455 get_bad_stack 456 bad_save_user_regs 457 bl do_not_used 458 459#ifdef CONFIG_USE_IRQ 460 461 .align 5 462irq: 463 get_irq_stack 464 irq_save_user_regs 465 bl do_irq 466 irq_restore_user_regs 467 468 .align 5 469fiq: 470 get_fiq_stack 471 /* someone ought to write a more effiction fiq_save_user_regs */ 472 irq_save_user_regs 473 bl do_fiq 474 irq_restore_user_regs 475 476#else 477 478 .align 5 479irq: 480 get_bad_stack 481 bad_save_user_regs 482 bl do_irq 483 484 .align 5 485fiq: 486 get_bad_stack 487 bad_save_user_regs 488 bl do_fiq 489 490#endif 491 492 .align 5 493.globl reset_cpu 494reset_cpu: 495 ldr r0, RST_BASE 496 mov r1, #0x0 @ set bit 3-0 ... 497 str r1, [r0, #RCSR] @ ... to clear in RCSR 498 mov r1, #0x1 499 str r1, [r0, #RSRR] @ and perform reset 500 b reset_cpu @ silly, but repeat endlessly 501