1/* 2 * armboot - Startup Code for SA1100 CPU 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (c) 2001 Alex Züpke <azu@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <asm-offsets.h> 29#include <config.h> 30#include <version.h> 31 32/* 33 ************************************************************************* 34 * 35 * Jump vector table as in table 3.1 in [1] 36 * 37 ************************************************************************* 38 */ 39 40 41.globl _start 42_start: b reset 43 ldr pc, _undefined_instruction 44 ldr pc, _software_interrupt 45 ldr pc, _prefetch_abort 46 ldr pc, _data_abort 47 ldr pc, _not_used 48 ldr pc, _irq 49 ldr pc, _fiq 50 51_undefined_instruction: .word undefined_instruction 52_software_interrupt: .word software_interrupt 53_prefetch_abort: .word prefetch_abort 54_data_abort: .word data_abort 55_not_used: .word not_used 56_irq: .word irq 57_fiq: .word fiq 58 59 .balignl 16,0xdeadbeef 60 61 62/* 63 ************************************************************************* 64 * 65 * Startup Code (reset vector) 66 * 67 * do important init only if we don't start from memory! 68 * relocate armboot to ram 69 * setup stack 70 * jump to second stage 71 * 72 ************************************************************************* 73 */ 74 75.globl _TEXT_BASE 76_TEXT_BASE: 77 .word CONFIG_SYS_TEXT_BASE 78 79/* 80 * These are defined in the board-specific linker script. 81 * Subtracting _start from them lets the linker put their 82 * relative position in the executable instead of leaving 83 * them null. 84 */ 85.globl _bss_start_ofs 86_bss_start_ofs: 87 .word __bss_start - _start 88 89.globl _bss_end_ofs 90_bss_end_ofs: 91 .word __bss_end__ - _start 92 93.globl _end_ofs 94_end_ofs: 95 .word _end - _start 96 97#ifdef CONFIG_USE_IRQ 98/* IRQ stack memory (calculated at run-time) */ 99.globl IRQ_STACK_START 100IRQ_STACK_START: 101 .word 0x0badc0de 102 103/* IRQ stack memory (calculated at run-time) */ 104.globl FIQ_STACK_START 105FIQ_STACK_START: 106 .word 0x0badc0de 107#endif 108 109/* IRQ stack memory (calculated at run-time) + 8 bytes */ 110.globl IRQ_STACK_START_IN 111IRQ_STACK_START_IN: 112 .word 0x0badc0de 113 114/* 115 * the actual reset code 116 */ 117 118reset: 119 /* 120 * set the cpu to SVC32 mode 121 */ 122 mrs r0,cpsr 123 bic r0,r0,#0x1f 124 orr r0,r0,#0xd3 125 msr cpsr,r0 126 127 /* 128 * we do sys-critical inits only at reboot, 129 * not when booting from ram! 130 */ 131#ifndef CONFIG_SKIP_LOWLEVEL_INIT 132 bl cpu_init_crit 133#endif 134 135/* Set stackpointer in internal RAM to call board_init_f */ 136call_board_init_f: 137 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 138 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 139 ldr r0,=0x00000000 140 bl board_init_f 141 142/*------------------------------------------------------------------------------*/ 143 144/* 145 * void relocate_code (addr_sp, gd, addr_moni) 146 * 147 * This "function" does not return, instead it continues in RAM 148 * after relocating the monitor code. 149 * 150 */ 151 .globl relocate_code 152relocate_code: 153 mov r4, r0 /* save addr_sp */ 154 mov r5, r1 /* save addr of gd */ 155 mov r6, r2 /* save addr of destination */ 156 157 /* Set up the stack */ 158stack_setup: 159 mov sp, r4 160 161 adr r0, _start 162 cmp r0, r6 163 beq clear_bss /* skip relocation */ 164 mov r1, r6 /* r1 <- scratch for copy_loop */ 165 ldr r3, _bss_start_ofs 166 add r2, r0, r3 /* r2 <- source end address */ 167 168copy_loop: 169 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 170 stmia r1!, {r9-r10} /* copy to target address [r1] */ 171 cmp r0, r2 /* until source end address [r2] */ 172 blo copy_loop 173 174#ifndef CONFIG_SPL_BUILD 175 /* 176 * fix .rel.dyn relocations 177 */ 178 ldr r0, _TEXT_BASE /* r0 <- Text base */ 179 sub r9, r6, r0 /* r9 <- relocation offset */ 180 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 181 add r10, r10, r0 /* r10 <- sym table in FLASH */ 182 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 183 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 184 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 185 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 186fixloop: 187 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 188 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 189 ldr r1, [r2, #4] 190 and r7, r1, #0xff 191 cmp r7, #23 /* relative fixup? */ 192 beq fixrel 193 cmp r7, #2 /* absolute fixup? */ 194 beq fixabs 195 /* ignore unknown type of fixup */ 196 b fixnext 197fixabs: 198 /* absolute fix: set location to (offset) symbol value */ 199 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 200 add r1, r10, r1 /* r1 <- address of symbol in table */ 201 ldr r1, [r1, #4] /* r1 <- symbol value */ 202 add r1, r1, r9 /* r1 <- relocated sym addr */ 203 b fixnext 204fixrel: 205 /* relative fix: increase location by offset */ 206 ldr r1, [r0] 207 add r1, r1, r9 208fixnext: 209 str r1, [r0] 210 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 211 cmp r2, r3 212 blo fixloop 213#endif 214 215clear_bss: 216#ifndef CONFIG_SPL_BUILD 217 ldr r0, _bss_start_ofs 218 ldr r1, _bss_end_ofs 219 mov r4, r6 /* reloc addr */ 220 add r0, r0, r4 221 add r1, r1, r4 222 mov r2, #0x00000000 /* clear */ 223 224clbss_l:cmp r0, r1 /* clear loop... */ 225 bhs clbss_e /* if reached end of bss, exit */ 226 str r2, [r0] 227 add r0, r0, #4 228 b clbss_l 229clbss_e: 230#endif 231 232/* 233 * We are done. Do not return, instead branch to second part of board 234 * initialization, now running from RAM. 235 */ 236 ldr r0, _board_init_r_ofs 237 adr r1, _start 238 add lr, r0, r1 239 add lr, lr, r9 240 /* setup parameters for board_init_r */ 241 mov r0, r5 /* gd_t */ 242 mov r1, r6 /* dest_addr */ 243 /* jump to it ... */ 244 mov pc, lr 245 246_board_init_r_ofs: 247 .word board_init_r - _start 248 249_rel_dyn_start_ofs: 250 .word __rel_dyn_start - _start 251_rel_dyn_end_ofs: 252 .word __rel_dyn_end - _start 253_dynsym_start_ofs: 254 .word __dynsym_start - _start 255 256/* 257 ************************************************************************* 258 * 259 * CPU_init_critical registers 260 * 261 * setup important registers 262 * setup memory timing 263 * 264 ************************************************************************* 265 */ 266 267 268/* Interrupt-Controller base address */ 269IC_BASE: .word 0x90050000 270#define ICMR 0x04 271 272 273/* Reset-Controller */ 274RST_BASE: .word 0x90030000 275#define RSRR 0x00 276#define RCSR 0x04 277 278 279/* PWR */ 280PWR_BASE: .word 0x90020000 281#define PSPR 0x08 282#define PPCR 0x14 283cpuspeed: .word CONFIG_SYS_CPUSPEED 284 285 286cpu_init_crit: 287 /* 288 * mask all IRQs 289 */ 290 ldr r0, IC_BASE 291 mov r1, #0x00 292 str r1, [r0, #ICMR] 293 294 /* set clock speed */ 295 ldr r0, PWR_BASE 296 ldr r1, cpuspeed 297 str r1, [r0, #PPCR] 298 299 /* 300 * before relocating, we have to setup RAM timing 301 * because memory timing is board-dependend, you will 302 * find a lowlevel_init.S in your board directory. 303 */ 304 mov ip, lr 305 bl lowlevel_init 306 mov lr, ip 307 308 /* 309 * disable MMU stuff and enable I-cache 310 */ 311 mrc p15,0,r0,c1,c0 312 bic r0, r0, #0x00002000 @ clear bit 13 (X) 313 bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM) 314 orr r0, r0, #0x00001000 @ set bit 12 (I) Icache 315 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 316 mcr p15,0,r0,c1,c0 317 318 /* 319 * flush v4 I/D caches 320 */ 321 mov r0, #0 322 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ 323 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ 324 325 mov pc, lr 326 327 328/* 329 ************************************************************************* 330 * 331 * Interrupt handling 332 * 333 ************************************************************************* 334 */ 335 336@ 337@ IRQ stack frame. 338@ 339#define S_FRAME_SIZE 72 340 341#define S_OLD_R0 68 342#define S_PSR 64 343#define S_PC 60 344#define S_LR 56 345#define S_SP 52 346 347#define S_IP 48 348#define S_FP 44 349#define S_R10 40 350#define S_R9 36 351#define S_R8 32 352#define S_R7 28 353#define S_R6 24 354#define S_R5 20 355#define S_R4 16 356#define S_R3 12 357#define S_R2 8 358#define S_R1 4 359#define S_R0 0 360 361#define MODE_SVC 0x13 362#define I_BIT 0x80 363 364/* 365 * use bad_save_user_regs for abort/prefetch/undef/swi ... 366 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 367 */ 368 369 .macro bad_save_user_regs 370 sub sp, sp, #S_FRAME_SIZE 371 stmia sp, {r0 - r12} @ Calling r0-r12 372 add r8, sp, #S_PC 373 374 ldr r2, IRQ_STACK_START_IN 375 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 376 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC 377 378 add r5, sp, #S_SP 379 mov r1, lr 380 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r 381 mov r0, sp 382 .endm 383 384 .macro irq_save_user_regs 385 sub sp, sp, #S_FRAME_SIZE 386 stmia sp, {r0 - r12} @ Calling r0-r12 387 add r8, sp, #S_PC 388 stmdb r8, {sp, lr}^ @ Calling SP, LR 389 str lr, [r8, #0] @ Save calling PC 390 mrs r6, spsr 391 str r6, [r8, #4] @ Save CPSR 392 str r0, [r8, #8] @ Save OLD_R0 393 mov r0, sp 394 .endm 395 396 .macro irq_restore_user_regs 397 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 398 mov r0, r0 399 ldr lr, [sp, #S_PC] @ Get PC 400 add sp, sp, #S_FRAME_SIZE 401 subs pc, lr, #4 @ return & move spsr_svc into cpsr 402 .endm 403 404 .macro get_bad_stack 405 ldr r13, IRQ_STACK_START_IN @ setup our mode stack 406 407 str lr, [r13] @ save caller lr / spsr 408 mrs lr, spsr 409 str lr, [r13, #4] 410 411 mov r13, #MODE_SVC @ prepare SVC-Mode 412 msr spsr_c, r13 413 mov lr, pc 414 movs pc, lr 415 .endm 416 417 .macro get_irq_stack @ setup IRQ stack 418 ldr sp, IRQ_STACK_START 419 .endm 420 421 .macro get_fiq_stack @ setup FIQ stack 422 ldr sp, FIQ_STACK_START 423 .endm 424 425/* 426 * exception handlers 427 */ 428 .align 5 429undefined_instruction: 430 get_bad_stack 431 bad_save_user_regs 432 bl do_undefined_instruction 433 434 .align 5 435software_interrupt: 436 get_bad_stack 437 bad_save_user_regs 438 bl do_software_interrupt 439 440 .align 5 441prefetch_abort: 442 get_bad_stack 443 bad_save_user_regs 444 bl do_prefetch_abort 445 446 .align 5 447data_abort: 448 get_bad_stack 449 bad_save_user_regs 450 bl do_data_abort 451 452 .align 5 453not_used: 454 get_bad_stack 455 bad_save_user_regs 456 bl do_not_used 457 458#ifdef CONFIG_USE_IRQ 459 460 .align 5 461irq: 462 get_irq_stack 463 irq_save_user_regs 464 bl do_irq 465 irq_restore_user_regs 466 467 .align 5 468fiq: 469 get_fiq_stack 470 /* someone ought to write a more effiction fiq_save_user_regs */ 471 irq_save_user_regs 472 bl do_fiq 473 irq_restore_user_regs 474 475#else 476 477 .align 5 478irq: 479 get_bad_stack 480 bad_save_user_regs 481 bl do_irq 482 483 .align 5 484fiq: 485 get_bad_stack 486 bad_save_user_regs 487 bl do_fiq 488 489#endif 490 491 .align 5 492.globl reset_cpu 493reset_cpu: 494 ldr r0, RST_BASE 495 mov r1, #0x0 @ set bit 3-0 ... 496 str r1, [r0, #RCSR] @ ... to clear in RCSR 497 mov r1, #0x1 498 str r1, [r0, #RSRR] @ and perform reset 499 b reset_cpu @ silly, but repeat endlessly 500