1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * armboot - Startup Code for XScale CPU-core 4 * 5 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 6 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 7 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 8 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 9 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 10 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 11 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 12 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 13 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 14 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 15 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 16 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 17 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 18 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 19 */ 20 21#include <asm-offsets.h> 22#include <config.h> 23 24/* 25 ************************************************************************* 26 * 27 * Startup Code (reset vector) 28 * 29 * do important init only if we don't start from memory! 30 * setup Memory and board specific bits prior to relocation. 31 * relocate armboot to ram 32 * setup stack 33 * 34 ************************************************************************* 35 */ 36 37 .globl reset 38 39reset: 40 /* 41 * set the cpu to SVC32 mode 42 */ 43 mrs r0,cpsr 44 bic r0,r0,#0x1f 45 orr r0,r0,#0xd3 46 msr cpsr,r0 47 48#ifndef CONFIG_SKIP_LOWLEVEL_INIT 49 bl cpu_init_crit 50#endif 51 52#ifdef CONFIG_CPU_PXA25X 53 bl lock_cache_for_stack 54#endif 55#ifdef CONFIG_CPU_PXA27X 56 /* 57 * enable clock for SRAM 58 */ 59 ldr r0,=CKEN 60 ldr r1,[r0] 61 orr r1,r1,#(1 << 20) 62 str r1,[r0] 63#endif 64 bl _main 65 66/*------------------------------------------------------------------------------*/ 67 68 .globl c_runtime_cpu_setup 69c_runtime_cpu_setup: 70 71#ifdef CONFIG_CPU_PXA25X 72 /* 73 * Unlock (actually, disable) the cache now that board_init_f 74 * is done. We could do this earlier but we would need to add 75 * a new C runtime hook, whereas c_runtime_cpu_setup already 76 * exists. 77 * As this routine is just a call to cpu_init_crit, let us 78 * tail-optimize and do a simple branch here. 79 */ 80 b cpu_init_crit 81#else 82 bx lr 83#endif 84 85/* 86 ************************************************************************* 87 * 88 * CPU_init_critical registers 89 * 90 * setup important registers 91 * setup memory timing 92 * 93 ************************************************************************* 94 */ 95#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 96cpu_init_crit: 97 /* 98 * flush v4 I/D caches 99 */ 100 mov r0, #0 101 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 102 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 103 104 /* 105 * disable MMU stuff and caches 106 */ 107 mrc p15, 0, r0, c1, c0, 0 108 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) 109 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 110 orr r0, r0, #0x00000002 @ set bit 1 (A) Align 111 mcr p15, 0, r0, c1, c0, 0 112 113 mov pc, lr /* back to my caller */ 114#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 115 116/* 117 * Enable MMU to use DCache as DRAM. 118 * 119 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 120 * other possible memory available to hold stack. 121 */ 122#ifdef CONFIG_CPU_PXA25X 123.macro CPWAIT reg 124 mrc p15, 0, \reg, c2, c0, 0 125 mov \reg, \reg 126 sub pc, pc, #4 127.endm 128lock_cache_for_stack: 129 /* Domain access -- enable for all CPs */ 130 ldr r0, =0x0000ffff 131 mcr p15, 0, r0, c3, c0, 0 132 133 /* Point TTBR to MMU table */ 134 ldr r0, =mmutable 135 mcr p15, 0, r0, c2, c0, 0 136 137 /* Kick in MMU, ICache, DCache, BTB */ 138 mrc p15, 0, r0, c1, c0, 0 139 bic r0, #0x1b00 140 bic r0, #0x0087 141 orr r0, #0x1800 142 orr r0, #0x0005 143 mcr p15, 0, r0, c1, c0, 0 144 CPWAIT r0 145 146 /* Unlock Icache, Dcache */ 147 mcr p15, 0, r0, c9, c1, 1 148 mcr p15, 0, r0, c9, c2, 1 149 150 /* Flush Icache, Dcache, BTB */ 151 mcr p15, 0, r0, c7, c7, 0 152 153 /* Unlock I-TLB, D-TLB */ 154 mcr p15, 0, r0, c10, c4, 1 155 mcr p15, 0, r0, c10, c8, 1 156 157 /* Flush TLB */ 158 mcr p15, 0, r0, c8, c7, 0 159 160 /* Allocate 4096 bytes of Dcache as RAM */ 161 162 /* Drain pending loads and stores */ 163 mcr p15, 0, r0, c7, c10, 4 164 165 mov r4, #0x00 166 mov r5, #0x00 167 mov r2, #0x01 168 mcr p15, 0, r0, c9, c2, 0 169 CPWAIT r0 170 171 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 172 mov r0, #128 173 ldr r1, =0xfffff000 174 175alloc: 176 mcr p15, 0, r1, c7, c2, 5 177 /* Drain pending loads and stores */ 178 mcr p15, 0, r0, c7, c10, 4 179 strd r4, [r1], #8 180 strd r4, [r1], #8 181 strd r4, [r1], #8 182 strd r4, [r1], #8 183 subs r0, #0x01 184 bne alloc 185 /* Drain pending loads and stores */ 186 mcr p15, 0, r0, c7, c10, 4 187 mov r2, #0x00 188 mcr p15, 0, r2, c9, c2, 0 189 CPWAIT r0 190 191 mov pc, lr 192 193.section .mmutable, "a" 194mmutable: 195 .align 14 196 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 197 .set __base, 0 198 .rept 0xfff 199 .word (__base << 20) | 0xc12 200 .set __base, __base + 1 201 .endr 202 203 /* 0xfff00000 : 1:1, cached mapping */ 204 .word (0xfff << 20) | 0x1c1e 205#endif /* CONFIG_CPU_PXA25X */ 206