1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22#include <asm-offsets.h> 23#include <config.h> 24 25/* 26 ************************************************************************* 27 * 28 * Startup Code (reset vector) 29 * 30 * do important init only if we don't start from memory! 31 * setup Memory and board specific bits prior to relocation. 32 * relocate armboot to ram 33 * setup stack 34 * 35 ************************************************************************* 36 */ 37 38 .globl reset 39 40reset: 41 /* 42 * set the cpu to SVC32 mode 43 */ 44 mrs r0,cpsr 45 bic r0,r0,#0x1f 46 orr r0,r0,#0xd3 47 msr cpsr,r0 48 49#ifndef CONFIG_SKIP_LOWLEVEL_INIT 50 bl cpu_init_crit 51#endif 52 53#ifdef CONFIG_CPU_PXA25X 54 bl lock_cache_for_stack 55#endif 56#ifdef CONFIG_CPU_PXA27X 57 /* 58 * enable clock for SRAM 59 */ 60 ldr r0,=CKEN 61 ldr r1,[r0] 62 orr r1,r1,#(1 << 20) 63 str r1,[r0] 64#endif 65 bl _main 66 67/*------------------------------------------------------------------------------*/ 68 69 .globl c_runtime_cpu_setup 70c_runtime_cpu_setup: 71 72#ifdef CONFIG_CPU_PXA25X 73 /* 74 * Unlock (actually, disable) the cache now that board_init_f 75 * is done. We could do this earlier but we would need to add 76 * a new C runtime hook, whereas c_runtime_cpu_setup already 77 * exists. 78 * As this routine is just a call to cpu_init_crit, let us 79 * tail-optimize and do a simple branch here. 80 */ 81 b cpu_init_crit 82#else 83 bx lr 84#endif 85 86/* 87 ************************************************************************* 88 * 89 * CPU_init_critical registers 90 * 91 * setup important registers 92 * setup memory timing 93 * 94 ************************************************************************* 95 */ 96#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 97cpu_init_crit: 98 /* 99 * flush v4 I/D caches 100 */ 101 mov r0, #0 102 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 103 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 104 105 /* 106 * disable MMU stuff and caches 107 */ 108 mrc p15, 0, r0, c1, c0, 0 109 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) 110 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 111 orr r0, r0, #0x00000002 @ set bit 1 (A) Align 112 mcr p15, 0, r0, c1, c0, 0 113 114 mov pc, lr /* back to my caller */ 115#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 116 117/* 118 * Enable MMU to use DCache as DRAM. 119 * 120 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 121 * other possible memory available to hold stack. 122 */ 123#ifdef CONFIG_CPU_PXA25X 124.macro CPWAIT reg 125 mrc p15, 0, \reg, c2, c0, 0 126 mov \reg, \reg 127 sub pc, pc, #4 128.endm 129lock_cache_for_stack: 130 /* Domain access -- enable for all CPs */ 131 ldr r0, =0x0000ffff 132 mcr p15, 0, r0, c3, c0, 0 133 134 /* Point TTBR to MMU table */ 135 ldr r0, =mmutable 136 mcr p15, 0, r0, c2, c0, 0 137 138 /* Kick in MMU, ICache, DCache, BTB */ 139 mrc p15, 0, r0, c1, c0, 0 140 bic r0, #0x1b00 141 bic r0, #0x0087 142 orr r0, #0x1800 143 orr r0, #0x0005 144 mcr p15, 0, r0, c1, c0, 0 145 CPWAIT r0 146 147 /* Unlock Icache, Dcache */ 148 mcr p15, 0, r0, c9, c1, 1 149 mcr p15, 0, r0, c9, c2, 1 150 151 /* Flush Icache, Dcache, BTB */ 152 mcr p15, 0, r0, c7, c7, 0 153 154 /* Unlock I-TLB, D-TLB */ 155 mcr p15, 0, r0, c10, c4, 1 156 mcr p15, 0, r0, c10, c8, 1 157 158 /* Flush TLB */ 159 mcr p15, 0, r0, c8, c7, 0 160 161 /* Allocate 4096 bytes of Dcache as RAM */ 162 163 /* Drain pending loads and stores */ 164 mcr p15, 0, r0, c7, c10, 4 165 166 mov r4, #0x00 167 mov r5, #0x00 168 mov r2, #0x01 169 mcr p15, 0, r0, c9, c2, 0 170 CPWAIT r0 171 172 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 173 mov r0, #128 174 ldr r1, =0xfffff000 175 176alloc: 177 mcr p15, 0, r1, c7, c2, 5 178 /* Drain pending loads and stores */ 179 mcr p15, 0, r0, c7, c10, 4 180 strd r4, [r1], #8 181 strd r4, [r1], #8 182 strd r4, [r1], #8 183 strd r4, [r1], #8 184 subs r0, #0x01 185 bne alloc 186 /* Drain pending loads and stores */ 187 mcr p15, 0, r0, c7, c10, 4 188 mov r2, #0x00 189 mcr p15, 0, r2, c9, c2, 0 190 CPWAIT r0 191 192 mov pc, lr 193 194.section .mmutable, "a" 195mmutable: 196 .align 14 197 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 198 .set __base, 0 199 .rept 0xfff 200 .word (__base << 20) | 0xc12 201 .set __base, __base + 1 202 .endr 203 204 /* 0xfff00000 : 1:1, cached mapping */ 205 .word (0xfff << 20) | 0x1c1e 206#endif /* CONFIG_CPU_PXA25X */ 207