1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22#include <asm-offsets.h> 23#include <config.h> 24#include <version.h> 25 26/* 27 ************************************************************************* 28 * 29 * Startup Code (reset vector) 30 * 31 * do important init only if we don't start from memory! 32 * setup Memory and board specific bits prior to relocation. 33 * relocate armboot to ram 34 * setup stack 35 * 36 ************************************************************************* 37 */ 38 39 .globl reset 40 41reset: 42 /* 43 * set the cpu to SVC32 mode 44 */ 45 mrs r0,cpsr 46 bic r0,r0,#0x1f 47 orr r0,r0,#0xd3 48 msr cpsr,r0 49 50#ifndef CONFIG_SKIP_LOWLEVEL_INIT 51 bl cpu_init_crit 52#endif 53 54#ifdef CONFIG_CPU_PXA25X 55 bl lock_cache_for_stack 56#endif 57 58 bl _main 59 60/*------------------------------------------------------------------------------*/ 61 62 .globl c_runtime_cpu_setup 63c_runtime_cpu_setup: 64 65#ifdef CONFIG_CPU_PXA25X 66 /* 67 * Unlock (actually, disable) the cache now that board_init_f 68 * is done. We could do this earlier but we would need to add 69 * a new C runtime hook, whereas c_runtime_cpu_setup already 70 * exists. 71 * As this routine is just a call to cpu_init_crit, let us 72 * tail-optimize and do a simple branch here. 73 */ 74 b cpu_init_crit 75#else 76 bx lr 77#endif 78 79/* 80 ************************************************************************* 81 * 82 * CPU_init_critical registers 83 * 84 * setup important registers 85 * setup memory timing 86 * 87 ************************************************************************* 88 */ 89#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 90cpu_init_crit: 91 /* 92 * flush v4 I/D caches 93 */ 94 mov r0, #0 95 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 96 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 97 98 /* 99 * disable MMU stuff and caches 100 */ 101 mrc p15, 0, r0, c1, c0, 0 102 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) 103 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 104 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 105 mcr p15, 0, r0, c1, c0, 0 106 107 mov pc, lr /* back to my caller */ 108#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 109 110/* 111 * Enable MMU to use DCache as DRAM. 112 * 113 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 114 * other possible memory available to hold stack. 115 */ 116#ifdef CONFIG_CPU_PXA25X 117.macro CPWAIT reg 118 mrc p15, 0, \reg, c2, c0, 0 119 mov \reg, \reg 120 sub pc, pc, #4 121.endm 122lock_cache_for_stack: 123 /* Domain access -- enable for all CPs */ 124 ldr r0, =0x0000ffff 125 mcr p15, 0, r0, c3, c0, 0 126 127 /* Point TTBR to MMU table */ 128 ldr r0, =mmutable 129 mcr p15, 0, r0, c2, c0, 0 130 131 /* Kick in MMU, ICache, DCache, BTB */ 132 mrc p15, 0, r0, c1, c0, 0 133 bic r0, #0x1b00 134 bic r0, #0x0087 135 orr r0, #0x1800 136 orr r0, #0x0005 137 mcr p15, 0, r0, c1, c0, 0 138 CPWAIT r0 139 140 /* Unlock Icache, Dcache */ 141 mcr p15, 0, r0, c9, c1, 1 142 mcr p15, 0, r0, c9, c2, 1 143 144 /* Flush Icache, Dcache, BTB */ 145 mcr p15, 0, r0, c7, c7, 0 146 147 /* Unlock I-TLB, D-TLB */ 148 mcr p15, 0, r0, c10, c4, 1 149 mcr p15, 0, r0, c10, c8, 1 150 151 /* Flush TLB */ 152 mcr p15, 0, r0, c8, c7, 0 153 154 /* Allocate 4096 bytes of Dcache as RAM */ 155 156 /* Drain pending loads and stores */ 157 mcr p15, 0, r0, c7, c10, 4 158 159 mov r4, #0x00 160 mov r5, #0x00 161 mov r2, #0x01 162 mcr p15, 0, r0, c9, c2, 0 163 CPWAIT r0 164 165 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 166 mov r0, #128 167 ldr r1, =0xfffff000 168 169alloc: 170 mcr p15, 0, r1, c7, c2, 5 171 /* Drain pending loads and stores */ 172 mcr p15, 0, r0, c7, c10, 4 173 strd r4, [r1], #8 174 strd r4, [r1], #8 175 strd r4, [r1], #8 176 strd r4, [r1], #8 177 subs r0, #0x01 178 bne alloc 179 /* Drain pending loads and stores */ 180 mcr p15, 0, r0, c7, c10, 4 181 mov r2, #0x00 182 mcr p15, 0, r2, c9, c2, 0 183 CPWAIT r0 184 185 mov pc, lr 186 187.section .mmutable, "a" 188mmutable: 189 .align 14 190 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 191 .set __base, 0 192 .rept 0xfff 193 .word (__base << 20) | 0xc12 194 .set __base, __base + 1 195 .endr 196 197 /* 0xfff00000 : 1:1, cached mapping */ 198 .word (0xfff << 20) | 0x1c1e 199#endif /* CONFIG_CPU_PXA25X */ 200