1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * SPDX-License-Identifier: GPL-2.0+ 20 */ 21 22#include <asm-offsets.h> 23#include <config.h> 24 25/* 26 ************************************************************************* 27 * 28 * Startup Code (reset vector) 29 * 30 * do important init only if we don't start from memory! 31 * setup Memory and board specific bits prior to relocation. 32 * relocate armboot to ram 33 * setup stack 34 * 35 ************************************************************************* 36 */ 37 38 .globl reset 39 40reset: 41 /* 42 * set the cpu to SVC32 mode 43 */ 44 mrs r0,cpsr 45 bic r0,r0,#0x1f 46 orr r0,r0,#0xd3 47 msr cpsr,r0 48 49#ifndef CONFIG_SKIP_LOWLEVEL_INIT 50 bl cpu_init_crit 51#endif 52 53#ifdef CONFIG_CPU_PXA25X 54 bl lock_cache_for_stack 55#endif 56 57 bl _main 58 59/*------------------------------------------------------------------------------*/ 60 61 .globl c_runtime_cpu_setup 62c_runtime_cpu_setup: 63 64#ifdef CONFIG_CPU_PXA25X 65 /* 66 * Unlock (actually, disable) the cache now that board_init_f 67 * is done. We could do this earlier but we would need to add 68 * a new C runtime hook, whereas c_runtime_cpu_setup already 69 * exists. 70 * As this routine is just a call to cpu_init_crit, let us 71 * tail-optimize and do a simple branch here. 72 */ 73 b cpu_init_crit 74#else 75 bx lr 76#endif 77 78/* 79 ************************************************************************* 80 * 81 * CPU_init_critical registers 82 * 83 * setup important registers 84 * setup memory timing 85 * 86 ************************************************************************* 87 */ 88#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 89cpu_init_crit: 90 /* 91 * flush v4 I/D caches 92 */ 93 mov r0, #0 94 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 95 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 96 97 /* 98 * disable MMU stuff and caches 99 */ 100 mrc p15, 0, r0, c1, c0, 0 101 bic r0, r0, #0x00003300 @ clear bits 13:12, 9:8 (--VI --RS) 102 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 103 orr r0, r0, #0x00000002 @ set bit 1 (A) Align 104 mcr p15, 0, r0, c1, c0, 0 105 106 mov pc, lr /* back to my caller */ 107#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 108 109/* 110 * Enable MMU to use DCache as DRAM. 111 * 112 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 113 * other possible memory available to hold stack. 114 */ 115#ifdef CONFIG_CPU_PXA25X 116.macro CPWAIT reg 117 mrc p15, 0, \reg, c2, c0, 0 118 mov \reg, \reg 119 sub pc, pc, #4 120.endm 121lock_cache_for_stack: 122 /* Domain access -- enable for all CPs */ 123 ldr r0, =0x0000ffff 124 mcr p15, 0, r0, c3, c0, 0 125 126 /* Point TTBR to MMU table */ 127 ldr r0, =mmutable 128 mcr p15, 0, r0, c2, c0, 0 129 130 /* Kick in MMU, ICache, DCache, BTB */ 131 mrc p15, 0, r0, c1, c0, 0 132 bic r0, #0x1b00 133 bic r0, #0x0087 134 orr r0, #0x1800 135 orr r0, #0x0005 136 mcr p15, 0, r0, c1, c0, 0 137 CPWAIT r0 138 139 /* Unlock Icache, Dcache */ 140 mcr p15, 0, r0, c9, c1, 1 141 mcr p15, 0, r0, c9, c2, 1 142 143 /* Flush Icache, Dcache, BTB */ 144 mcr p15, 0, r0, c7, c7, 0 145 146 /* Unlock I-TLB, D-TLB */ 147 mcr p15, 0, r0, c10, c4, 1 148 mcr p15, 0, r0, c10, c8, 1 149 150 /* Flush TLB */ 151 mcr p15, 0, r0, c8, c7, 0 152 153 /* Allocate 4096 bytes of Dcache as RAM */ 154 155 /* Drain pending loads and stores */ 156 mcr p15, 0, r0, c7, c10, 4 157 158 mov r4, #0x00 159 mov r5, #0x00 160 mov r2, #0x01 161 mcr p15, 0, r0, c9, c2, 0 162 CPWAIT r0 163 164 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 165 mov r0, #128 166 ldr r1, =0xfffff000 167 168alloc: 169 mcr p15, 0, r1, c7, c2, 5 170 /* Drain pending loads and stores */ 171 mcr p15, 0, r0, c7, c10, 4 172 strd r4, [r1], #8 173 strd r4, [r1], #8 174 strd r4, [r1], #8 175 strd r4, [r1], #8 176 subs r0, #0x01 177 bne alloc 178 /* Drain pending loads and stores */ 179 mcr p15, 0, r0, c7, c10, 4 180 mov r2, #0x00 181 mcr p15, 0, r2, c9, c2, 0 182 CPWAIT r0 183 184 mov pc, lr 185 186.section .mmutable, "a" 187mmutable: 188 .align 14 189 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 190 .set __base, 0 191 .rept 0xfff 192 .word (__base << 20) | 0xc12 193 .set __base, __base + 1 194 .endr 195 196 /* 0xfff00000 : 1:1, cached mapping */ 197 .word (0xfff << 20) | 0x1c1e 198#endif /* CONFIG_CPU_PXA25X */ 199