1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * See file CREDITS for list of people who contributed to this 20 * project. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License as 24 * published by the Free Software Foundation; either version 2 of 25 * the License, or (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 35 * MA 02111-1307 USA 36 */ 37 38#include <asm-offsets.h> 39#include <config.h> 40#include <version.h> 41 42#ifdef CONFIG_CPU_PXA25X 43#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) 44#error "Init SP address must be set to 0xfffff800 for PXA250" 45#endif 46#endif 47 48.globl _start 49_start: b reset 50#ifdef CONFIG_SPL_BUILD 51 ldr pc, _hang 52 ldr pc, _hang 53 ldr pc, _hang 54 ldr pc, _hang 55 ldr pc, _hang 56 ldr pc, _hang 57 ldr pc, _hang 58 59_hang: 60 .word do_hang 61 .word 0x12345678 62 .word 0x12345678 63 .word 0x12345678 64 .word 0x12345678 65 .word 0x12345678 66 .word 0x12345678 67 .word 0x12345678 /* now 16*4=64 */ 68#else 69 ldr pc, _undefined_instruction 70 ldr pc, _software_interrupt 71 ldr pc, _prefetch_abort 72 ldr pc, _data_abort 73 ldr pc, _not_used 74 ldr pc, _irq 75 ldr pc, _fiq 76 77_undefined_instruction: .word undefined_instruction 78_software_interrupt: .word software_interrupt 79_prefetch_abort: .word prefetch_abort 80_data_abort: .word data_abort 81_not_used: .word not_used 82_irq: .word irq 83_fiq: .word fiq 84_pad: .word 0x12345678 /* now 16*4=64 */ 85#endif /* CONFIG_SPL_BUILD */ 86.global _end_vect 87_end_vect: 88 89 .balignl 16,0xdeadbeef 90/* 91 ************************************************************************* 92 * 93 * Startup Code (reset vector) 94 * 95 * do important init only if we don't start from memory! 96 * setup Memory and board specific bits prior to relocation. 97 * relocate armboot to ram 98 * setup stack 99 * 100 ************************************************************************* 101 */ 102 103.globl _TEXT_BASE 104_TEXT_BASE: 105#ifdef CONFIG_SPL_BUILD 106 .word CONFIG_SPL_TEXT_BASE 107#else 108 .word CONFIG_SYS_TEXT_BASE 109#endif 110 111/* 112 * These are defined in the board-specific linker script. 113 * Subtracting _start from them lets the linker put their 114 * relative position in the executable instead of leaving 115 * them null. 116 */ 117.globl _bss_start_ofs 118_bss_start_ofs: 119 .word __bss_start - _start 120 121.globl _bss_end_ofs 122_bss_end_ofs: 123 .word __bss_end__ - _start 124 125.globl _end_ofs 126_end_ofs: 127 .word _end - _start 128 129#ifdef CONFIG_USE_IRQ 130/* IRQ stack memory (calculated at run-time) */ 131.globl IRQ_STACK_START 132IRQ_STACK_START: 133 .word 0x0badc0de 134 135/* IRQ stack memory (calculated at run-time) */ 136.globl FIQ_STACK_START 137FIQ_STACK_START: 138 .word 0x0badc0de 139#endif 140 141/* IRQ stack memory (calculated at run-time) + 8 bytes */ 142.globl IRQ_STACK_START_IN 143IRQ_STACK_START_IN: 144 .word 0x0badc0de 145 146/* 147 * the actual reset code 148 */ 149 150reset: 151 /* 152 * set the cpu to SVC32 mode 153 */ 154 mrs r0,cpsr 155 bic r0,r0,#0x1f 156 orr r0,r0,#0xd3 157 msr cpsr,r0 158 159#ifndef CONFIG_SKIP_LOWLEVEL_INIT 160 bl cpu_init_crit 161#endif 162 163#ifdef CONFIG_CPU_PXA25X 164 bl lock_cache_for_stack 165#endif 166 167/* Set stackpointer in internal RAM to call board_init_f */ 168call_board_init_f: 169 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 170 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 171 ldr r0, =0x00000000 172 bl board_init_f 173 174/*------------------------------------------------------------------------------*/ 175#ifndef CONFIG_SPL_BUILD 176/* 177 * void relocate_code (addr_sp, gd, addr_moni) 178 * 179 * This "function" does not return, instead it continues in RAM 180 * after relocating the monitor code. 181 * 182 */ 183 .globl relocate_code 184relocate_code: 185 mov r4, r0 /* save addr_sp */ 186 mov r5, r1 /* save addr of gd */ 187 mov r6, r2 /* save addr of destination */ 188 189 /* Set up the stack */ 190stack_setup: 191 mov sp, r4 192 193/* Disable the Dcache RAM lock for stack now */ 194#ifdef CONFIG_CPU_PXA25X 195 bl cpu_init_crit 196#endif 197 198 adr r0, _start 199 cmp r0, r6 200 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ 201 beq clear_bss /* skip relocation */ 202 mov r1, r6 /* r1 <- scratch for copy_loop */ 203 ldr r3, _bss_start_ofs 204 add r2, r0, r3 /* r2 <- source end address */ 205 206copy_loop: 207 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 208 stmia r1!, {r9-r10} /* copy to target address [r1] */ 209 cmp r0, r2 /* until source end address [r2] */ 210 blo copy_loop 211 212#ifndef CONFIG_SPL_BUILD 213 /* 214 * fix .rel.dyn relocations 215 */ 216 ldr r0, _TEXT_BASE /* r0 <- Text base */ 217 sub r9, r6, r0 /* r9 <- relocation offset */ 218 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 219 add r10, r10, r0 /* r10 <- sym table in FLASH */ 220 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 221 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 222 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 223 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 224fixloop: 225 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 226 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 227 ldr r1, [r2, #4] 228 and r7, r1, #0xff 229 cmp r7, #23 /* relative fixup? */ 230 beq fixrel 231 cmp r7, #2 /* absolute fixup? */ 232 beq fixabs 233 /* ignore unknown type of fixup */ 234 b fixnext 235fixabs: 236 /* absolute fix: set location to (offset) symbol value */ 237 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 238 add r1, r10, r1 /* r1 <- address of symbol in table */ 239 ldr r1, [r1, #4] /* r1 <- symbol value */ 240 add r1, r1, r9 /* r1 <- relocated sym addr */ 241 b fixnext 242fixrel: 243 /* relative fix: increase location by offset */ 244 ldr r1, [r0] 245 add r1, r1, r9 246fixnext: 247 str r1, [r0] 248 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 249 cmp r2, r3 250 blo fixloop 251#endif 252 253clear_bss: 254#ifndef CONFIG_SPL_BUILD 255 ldr r0, _bss_start_ofs 256 ldr r1, _bss_end_ofs 257 mov r4, r6 /* reloc addr */ 258 add r0, r0, r4 259 add r1, r1, r4 260 mov r2, #0x00000000 /* clear */ 261 262clbss_l:cmp r0, r1 /* clear loop... */ 263 bhs clbss_e /* if reached end of bss, exit */ 264 str r2, [r0] 265 add r0, r0, #4 266 b clbss_l 267clbss_e: 268#endif /* #ifndef CONFIG_SPL_BUILD */ 269 270/* 271 * We are done. Do not return, instead branch to second part of board 272 * initialization, now running from RAM. 273 */ 274#ifdef CONFIG_ONENAND_SPL 275 ldr r0, _onenand_boot_ofs 276 mov pc, r0 277 278_onenand_boot_ofs: 279 .word onenand_boot 280#else 281jump_2_ram: 282 ldr r0, _board_init_r_ofs 283 ldr r1, _TEXT_BASE 284 add lr, r0, r1 285 add lr, lr, r9 286 /* setup parameters for board_init_r */ 287 mov r0, r5 /* gd_t */ 288 mov r1, r6 /* dest_addr */ 289 /* jump to it ... */ 290 mov pc, lr 291 292_board_init_r_ofs: 293 .word board_init_r - _start 294#endif 295 296_rel_dyn_start_ofs: 297 .word __rel_dyn_start - _start 298_rel_dyn_end_ofs: 299 .word __rel_dyn_end - _start 300_dynsym_start_ofs: 301 .word __dynsym_start - _start 302#endif 303/* 304 ************************************************************************* 305 * 306 * CPU_init_critical registers 307 * 308 * setup important registers 309 * setup memory timing 310 * 311 ************************************************************************* 312 */ 313#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 314cpu_init_crit: 315 /* 316 * flush v4 I/D caches 317 */ 318 mov r0, #0 319 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 320 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 321 322 /* 323 * disable MMU stuff and caches 324 */ 325 mrc p15, 0, r0, c1, c0, 0 326 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 327 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 328 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 329 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 330 mcr p15, 0, r0, c1, c0, 0 331 332 mov pc, lr /* back to my caller */ 333#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 334 335#ifndef CONFIG_SPL_BUILD 336/* 337 ************************************************************************* 338 * 339 * Interrupt handling 340 * 341 ************************************************************************* 342 */ 343@ 344@ IRQ stack frame. 345@ 346#define S_FRAME_SIZE 72 347 348#define S_OLD_R0 68 349#define S_PSR 64 350#define S_PC 60 351#define S_LR 56 352#define S_SP 52 353 354#define S_IP 48 355#define S_FP 44 356#define S_R10 40 357#define S_R9 36 358#define S_R8 32 359#define S_R7 28 360#define S_R6 24 361#define S_R5 20 362#define S_R4 16 363#define S_R3 12 364#define S_R2 8 365#define S_R1 4 366#define S_R0 0 367 368#define MODE_SVC 0x13 369#define I_BIT 0x80 370 371/* 372 * use bad_save_user_regs for abort/prefetch/undef/swi ... 373 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 374 */ 375 376 .macro bad_save_user_regs 377 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 378 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 379 380 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 381 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 382 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 383 384 add r5, sp, #S_SP 385 mov r1, lr 386 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 387 mov r0, sp @ save current stack into r0 (param register) 388 .endm 389 390 .macro irq_save_user_regs 391 sub sp, sp, #S_FRAME_SIZE 392 stmia sp, {r0 - r12} @ Calling r0-r12 393 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 394 stmdb r8, {sp, lr}^ @ Calling SP, LR 395 str lr, [r8, #0] @ Save calling PC 396 mrs r6, spsr 397 str r6, [r8, #4] @ Save CPSR 398 str r0, [r8, #8] @ Save OLD_R0 399 mov r0, sp 400 .endm 401 402 .macro irq_restore_user_regs 403 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 404 mov r0, r0 405 ldr lr, [sp, #S_PC] @ Get PC 406 add sp, sp, #S_FRAME_SIZE 407 subs pc, lr, #4 @ return & move spsr_svc into cpsr 408 .endm 409 410 .macro get_bad_stack 411 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 412 413 str lr, [r13] @ save caller lr in position 0 of saved stack 414 mrs lr, spsr @ get the spsr 415 str lr, [r13, #4] @ save spsr in position 1 of saved stack 416 417 mov r13, #MODE_SVC @ prepare SVC-Mode 418 @ msr spsr_c, r13 419 msr spsr, r13 @ switch modes, make sure moves will execute 420 mov lr, pc @ capture return pc 421 movs pc, lr @ jump to next instruction & switch modes. 422 .endm 423 424 .macro get_bad_stack_swi 425 sub r13, r13, #4 @ space on current stack for scratch reg. 426 str r0, [r13] @ save R0's value. 427 ldr r0, IRQ_STACK_START_IN @ get data regions start 428 str lr, [r0] @ save caller lr in position 0 of saved stack 429 mrs r0, spsr @ get the spsr 430 str lr, [r0, #4] @ save spsr in position 1 of saved stack 431 ldr r0, [r13] @ restore r0 432 add r13, r13, #4 @ pop stack entry 433 .endm 434 435 .macro get_irq_stack @ setup IRQ stack 436 ldr sp, IRQ_STACK_START 437 .endm 438 439 .macro get_fiq_stack @ setup FIQ stack 440 ldr sp, FIQ_STACK_START 441 .endm 442#endif /* CONFIG_SPL_BUILD */ 443 444/* 445 * exception handlers 446 */ 447#ifdef CONFIG_SPL_BUILD 448 .align 5 449do_hang: 450 ldr sp, _TEXT_BASE /* use 32 words about stack */ 451 bl hang /* hang and never return */ 452#else /* !CONFIG_SPL_BUILD */ 453 .align 5 454undefined_instruction: 455 get_bad_stack 456 bad_save_user_regs 457 bl do_undefined_instruction 458 459 .align 5 460software_interrupt: 461 get_bad_stack_swi 462 bad_save_user_regs 463 bl do_software_interrupt 464 465 .align 5 466prefetch_abort: 467 get_bad_stack 468 bad_save_user_regs 469 bl do_prefetch_abort 470 471 .align 5 472data_abort: 473 get_bad_stack 474 bad_save_user_regs 475 bl do_data_abort 476 477 .align 5 478not_used: 479 get_bad_stack 480 bad_save_user_regs 481 bl do_not_used 482 483#ifdef CONFIG_USE_IRQ 484 485 .align 5 486irq: 487 get_irq_stack 488 irq_save_user_regs 489 bl do_irq 490 irq_restore_user_regs 491 492 .align 5 493fiq: 494 get_fiq_stack 495 /* someone ought to write a more effiction fiq_save_user_regs */ 496 irq_save_user_regs 497 bl do_fiq 498 irq_restore_user_regs 499 500#else 501 502 .align 5 503irq: 504 get_bad_stack 505 bad_save_user_regs 506 bl do_irq 507 508 .align 5 509fiq: 510 get_bad_stack 511 bad_save_user_regs 512 bl do_fiq 513 514#endif 515 .align 5 516#endif /* CONFIG_SPL_BUILD */ 517 518 519/* 520 * Enable MMU to use DCache as DRAM. 521 * 522 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 523 * other possible memory available to hold stack. 524 */ 525#ifdef CONFIG_CPU_PXA25X 526.macro CPWAIT reg 527 mrc p15, 0, \reg, c2, c0, 0 528 mov \reg, \reg 529 sub pc, pc, #4 530.endm 531lock_cache_for_stack: 532 /* Domain access -- enable for all CPs */ 533 ldr r0, =0x0000ffff 534 mcr p15, 0, r0, c3, c0, 0 535 536 /* Point TTBR to MMU table */ 537 ldr r0, =mmutable 538 mcr p15, 0, r0, c2, c0, 0 539 540 /* Kick in MMU, ICache, DCache, BTB */ 541 mrc p15, 0, r0, c1, c0, 0 542 bic r0, #0x1b00 543 bic r0, #0x0087 544 orr r0, #0x1800 545 orr r0, #0x0005 546 mcr p15, 0, r0, c1, c0, 0 547 CPWAIT r0 548 549 /* Unlock Icache, Dcache */ 550 mcr p15, 0, r0, c9, c1, 1 551 mcr p15, 0, r0, c9, c2, 1 552 553 /* Flush Icache, Dcache, BTB */ 554 mcr p15, 0, r0, c7, c7, 0 555 556 /* Unlock I-TLB, D-TLB */ 557 mcr p15, 0, r0, c10, c4, 1 558 mcr p15, 0, r0, c10, c8, 1 559 560 /* Flush TLB */ 561 mcr p15, 0, r0, c8, c7, 0 562 563 /* Allocate 4096 bytes of Dcache as RAM */ 564 565 /* Drain pending loads and stores */ 566 mcr p15, 0, r0, c7, c10, 4 567 568 mov r4, #0x00 569 mov r5, #0x00 570 mov r2, #0x01 571 mcr p15, 0, r0, c9, c2, 0 572 CPWAIT r0 573 574 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 575 mov r0, #128 576 ldr r1, =0xfffff000 577 578alloc: 579 mcr p15, 0, r1, c7, c2, 5 580 /* Drain pending loads and stores */ 581 mcr p15, 0, r0, c7, c10, 4 582 strd r4, [r1], #8 583 strd r4, [r1], #8 584 strd r4, [r1], #8 585 strd r4, [r1], #8 586 subs r0, #0x01 587 bne alloc 588 /* Drain pending loads and stores */ 589 mcr p15, 0, r0, c7, c10, 4 590 mov r2, #0x00 591 mcr p15, 0, r2, c9, c2, 0 592 CPWAIT r0 593 594 mov pc, lr 595 596.section .mmutable, "a" 597mmutable: 598 .align 14 599 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 600 .set __base, 0 601 .rept 0xfff 602 .word (__base << 20) | 0xc12 603 .set __base, __base + 1 604 .endr 605 606 /* 0xfff00000 : 1:1, cached mapping */ 607 .word (0xfff << 20) | 0x1c1e 608#endif /* CONFIG_CPU_PXA25X */ 609