1/* 2 * armboot - Startup Code for XScale CPU-core 3 * 4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de> 7 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de> 8 * Copyright (C) 2001 Marius Groger <mag@sysgo.de> 9 * Copyright (C) 2002 Alex Zupke <azu@sysgo.de> 10 * Copyright (C) 2002 Gary Jennejohn <garyj@denx.de> 11 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net> 12 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de> 13 * Copyright (C) 2003 Kshitij <kshitij@ti.com> 14 * Copyright (C) 2003 Richard Woodruff <r-woodruff2@ti.com> 15 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de> 16 * Copyright (C) 2004 Texas Instruments <r-woodruff2@ti.com> 17 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 18 * 19 * See file CREDITS for list of people who contributed to this 20 * project. 21 * 22 * This program is free software; you can redistribute it and/or 23 * modify it under the terms of the GNU General Public License as 24 * published by the Free Software Foundation; either version 2 of 25 * the License, or (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 35 * MA 02111-1307 USA 36 */ 37 38#include <asm-offsets.h> 39#include <config.h> 40#include <version.h> 41 42#ifdef CONFIG_CPU_PXA25X 43#if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800) 44#error "Init SP address must be set to 0xfffff800 for PXA250" 45#endif 46#endif 47 48.globl _start 49_start: b reset 50#ifdef CONFIG_SPL_BUILD 51 ldr pc, _hang 52 ldr pc, _hang 53 ldr pc, _hang 54 ldr pc, _hang 55 ldr pc, _hang 56 ldr pc, _hang 57 ldr pc, _hang 58 59_hang: 60 .word do_hang 61 .word 0x12345678 62 .word 0x12345678 63 .word 0x12345678 64 .word 0x12345678 65 .word 0x12345678 66 .word 0x12345678 67 .word 0x12345678 /* now 16*4=64 */ 68#else 69 ldr pc, _undefined_instruction 70 ldr pc, _software_interrupt 71 ldr pc, _prefetch_abort 72 ldr pc, _data_abort 73 ldr pc, _not_used 74 ldr pc, _irq 75 ldr pc, _fiq 76 77_undefined_instruction: .word undefined_instruction 78_software_interrupt: .word software_interrupt 79_prefetch_abort: .word prefetch_abort 80_data_abort: .word data_abort 81_not_used: .word not_used 82_irq: .word irq 83_fiq: .word fiq 84_pad: .word 0x12345678 /* now 16*4=64 */ 85#endif /* CONFIG_SPL_BUILD */ 86.global _end_vect 87_end_vect: 88 89 .balignl 16,0xdeadbeef 90/* 91 ************************************************************************* 92 * 93 * Startup Code (reset vector) 94 * 95 * do important init only if we don't start from memory! 96 * setup Memory and board specific bits prior to relocation. 97 * relocate armboot to ram 98 * setup stack 99 * 100 ************************************************************************* 101 */ 102 103.globl _TEXT_BASE 104_TEXT_BASE: 105#ifdef CONFIG_SPL_BUILD 106 .word CONFIG_SPL_TEXT_BASE 107#else 108 .word CONFIG_SYS_TEXT_BASE 109#endif 110 111/* 112 * These are defined in the board-specific linker script. 113 * Subtracting _start from them lets the linker put their 114 * relative position in the executable instead of leaving 115 * them null. 116 */ 117.globl _bss_start_ofs 118_bss_start_ofs: 119 .word __bss_start - _start 120 121.globl _bss_end_ofs 122_bss_end_ofs: 123 .word __bss_end__ - _start 124 125.globl _end_ofs 126_end_ofs: 127 .word _end - _start 128 129#ifdef CONFIG_USE_IRQ 130/* IRQ stack memory (calculated at run-time) */ 131.globl IRQ_STACK_START 132IRQ_STACK_START: 133 .word 0x0badc0de 134 135/* IRQ stack memory (calculated at run-time) */ 136.globl FIQ_STACK_START 137FIQ_STACK_START: 138 .word 0x0badc0de 139#endif 140 141/* IRQ stack memory (calculated at run-time) + 8 bytes */ 142.globl IRQ_STACK_START_IN 143IRQ_STACK_START_IN: 144 .word 0x0badc0de 145 146/* 147 * the actual reset code 148 */ 149 150reset: 151 /* 152 * set the cpu to SVC32 mode 153 */ 154 mrs r0,cpsr 155 bic r0,r0,#0x1f 156 orr r0,r0,#0xd3 157 msr cpsr,r0 158 159#ifndef CONFIG_SKIP_LOWLEVEL_INIT 160 bl cpu_init_crit 161#endif 162 163#ifdef CONFIG_CPU_PXA25X 164 bl lock_cache_for_stack 165#endif 166 167/* Set stackpointer in internal RAM to call board_init_f */ 168call_board_init_f: 169 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) 170 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ 171 ldr r0, =0x00000000 172 bl board_init_f 173 174/*------------------------------------------------------------------------------*/ 175#ifndef CONFIG_SPL_BUILD 176/* 177 * void relocate_code (addr_sp, gd, addr_moni) 178 * 179 * This "function" does not return, instead it continues in RAM 180 * after relocating the monitor code. 181 * 182 */ 183 .globl relocate_code 184relocate_code: 185 mov r4, r0 /* save addr_sp */ 186 mov r5, r1 /* save addr of gd */ 187 mov r6, r2 /* save addr of destination */ 188 189 /* Set up the stack */ 190stack_setup: 191 mov sp, r4 192 193/* Disable the Dcache RAM lock for stack now */ 194#ifdef CONFIG_CPU_PXA25X 195 bl cpu_init_crit 196#endif 197 198 adr r0, _start 199 cmp r0, r6 200 beq clear_bss /* skip relocation */ 201 mov r1, r6 /* r1 <- scratch for copy_loop */ 202 ldr r3, _bss_start_ofs 203 add r2, r0, r3 /* r2 <- source end address */ 204 205copy_loop: 206 ldmia r0!, {r9-r10} /* copy from source address [r0] */ 207 stmia r1!, {r9-r10} /* copy to target address [r1] */ 208 cmp r0, r2 /* until source end address [r2] */ 209 blo copy_loop 210 211#ifndef CONFIG_SPL_BUILD 212 /* 213 * fix .rel.dyn relocations 214 */ 215 ldr r0, _TEXT_BASE /* r0 <- Text base */ 216 sub r9, r6, r0 /* r9 <- relocation offset */ 217 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ 218 add r10, r10, r0 /* r10 <- sym table in FLASH */ 219 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ 220 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ 221 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ 222 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ 223fixloop: 224 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ 225 add r0, r0, r9 /* r0 <- location to fix up in RAM */ 226 ldr r1, [r2, #4] 227 and r7, r1, #0xff 228 cmp r7, #23 /* relative fixup? */ 229 beq fixrel 230 cmp r7, #2 /* absolute fixup? */ 231 beq fixabs 232 /* ignore unknown type of fixup */ 233 b fixnext 234fixabs: 235 /* absolute fix: set location to (offset) symbol value */ 236 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ 237 add r1, r10, r1 /* r1 <- address of symbol in table */ 238 ldr r1, [r1, #4] /* r1 <- symbol value */ 239 add r1, r1, r9 /* r1 <- relocated sym addr */ 240 b fixnext 241fixrel: 242 /* relative fix: increase location by offset */ 243 ldr r1, [r0] 244 add r1, r1, r9 245fixnext: 246 str r1, [r0] 247 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ 248 cmp r2, r3 249 blo fixloop 250#endif 251 252clear_bss: 253#ifndef CONFIG_SPL_BUILD 254 ldr r0, _bss_start_ofs 255 ldr r1, _bss_end_ofs 256 mov r4, r6 /* reloc addr */ 257 add r0, r0, r4 258 add r1, r1, r4 259 mov r2, #0x00000000 /* clear */ 260 261clbss_l:cmp r0, r1 /* clear loop... */ 262 bhs clbss_e /* if reached end of bss, exit */ 263 str r2, [r0] 264 add r0, r0, #4 265 b clbss_l 266clbss_e: 267#endif /* #ifndef CONFIG_SPL_BUILD */ 268 269/* 270 * We are done. Do not return, instead branch to second part of board 271 * initialization, now running from RAM. 272 */ 273#ifdef CONFIG_ONENAND_SPL 274 ldr r0, _onenand_boot_ofs 275 mov pc, r0 276 277_onenand_boot_ofs: 278 .word onenand_boot 279#else 280jump_2_ram: 281 ldr r0, _board_init_r_ofs 282 ldr r1, _TEXT_BASE 283 add lr, r0, r1 284 add lr, lr, r9 285 /* setup parameters for board_init_r */ 286 mov r0, r5 /* gd_t */ 287 mov r1, r6 /* dest_addr */ 288 /* jump to it ... */ 289 mov pc, lr 290 291_board_init_r_ofs: 292 .word board_init_r - _start 293#endif 294 295_rel_dyn_start_ofs: 296 .word __rel_dyn_start - _start 297_rel_dyn_end_ofs: 298 .word __rel_dyn_end - _start 299_dynsym_start_ofs: 300 .word __dynsym_start - _start 301#endif 302/* 303 ************************************************************************* 304 * 305 * CPU_init_critical registers 306 * 307 * setup important registers 308 * setup memory timing 309 * 310 ************************************************************************* 311 */ 312#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) 313cpu_init_crit: 314 /* 315 * flush v4 I/D caches 316 */ 317 mov r0, #0 318 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */ 319 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */ 320 321 /* 322 * disable MMU stuff and caches 323 */ 324 mrc p15, 0, r0, c1, c0, 0 325 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) 326 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) 327 orr r0, r0, #0x00000002 @ set bit 2 (A) Align 328 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache 329 mcr p15, 0, r0, c1, c0, 0 330 331 mov pc, lr /* back to my caller */ 332#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ 333 334#ifndef CONFIG_SPL_BUILD 335/* 336 ************************************************************************* 337 * 338 * Interrupt handling 339 * 340 ************************************************************************* 341 */ 342@ 343@ IRQ stack frame. 344@ 345#define S_FRAME_SIZE 72 346 347#define S_OLD_R0 68 348#define S_PSR 64 349#define S_PC 60 350#define S_LR 56 351#define S_SP 52 352 353#define S_IP 48 354#define S_FP 44 355#define S_R10 40 356#define S_R9 36 357#define S_R8 32 358#define S_R7 28 359#define S_R6 24 360#define S_R5 20 361#define S_R4 16 362#define S_R3 12 363#define S_R2 8 364#define S_R1 4 365#define S_R0 0 366 367#define MODE_SVC 0x13 368#define I_BIT 0x80 369 370/* 371 * use bad_save_user_regs for abort/prefetch/undef/swi ... 372 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling 373 */ 374 375 .macro bad_save_user_regs 376 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack 377 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 378 379 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack 380 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) 381 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack 382 383 add r5, sp, #S_SP 384 mov r1, lr 385 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr 386 mov r0, sp @ save current stack into r0 (param register) 387 .endm 388 389 .macro irq_save_user_regs 390 sub sp, sp, #S_FRAME_SIZE 391 stmia sp, {r0 - r12} @ Calling r0-r12 392 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good. 393 stmdb r8, {sp, lr}^ @ Calling SP, LR 394 str lr, [r8, #0] @ Save calling PC 395 mrs r6, spsr 396 str r6, [r8, #4] @ Save CPSR 397 str r0, [r8, #8] @ Save OLD_R0 398 mov r0, sp 399 .endm 400 401 .macro irq_restore_user_regs 402 ldmia sp, {r0 - lr}^ @ Calling r0 - lr 403 mov r0, r0 404 ldr lr, [sp, #S_PC] @ Get PC 405 add sp, sp, #S_FRAME_SIZE 406 subs pc, lr, #4 @ return & move spsr_svc into cpsr 407 .endm 408 409 .macro get_bad_stack 410 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) 411 412 str lr, [r13] @ save caller lr in position 0 of saved stack 413 mrs lr, spsr @ get the spsr 414 str lr, [r13, #4] @ save spsr in position 1 of saved stack 415 416 mov r13, #MODE_SVC @ prepare SVC-Mode 417 @ msr spsr_c, r13 418 msr spsr, r13 @ switch modes, make sure moves will execute 419 mov lr, pc @ capture return pc 420 movs pc, lr @ jump to next instruction & switch modes. 421 .endm 422 423 .macro get_bad_stack_swi 424 sub r13, r13, #4 @ space on current stack for scratch reg. 425 str r0, [r13] @ save R0's value. 426 ldr r0, IRQ_STACK_START_IN @ get data regions start 427 str lr, [r0] @ save caller lr in position 0 of saved stack 428 mrs r0, spsr @ get the spsr 429 str lr, [r0, #4] @ save spsr in position 1 of saved stack 430 ldr r0, [r13] @ restore r0 431 add r13, r13, #4 @ pop stack entry 432 .endm 433 434 .macro get_irq_stack @ setup IRQ stack 435 ldr sp, IRQ_STACK_START 436 .endm 437 438 .macro get_fiq_stack @ setup FIQ stack 439 ldr sp, FIQ_STACK_START 440 .endm 441#endif /* CONFIG_SPL_BUILD */ 442 443/* 444 * exception handlers 445 */ 446#ifdef CONFIG_SPL_BUILD 447 .align 5 448do_hang: 449 ldr sp, _TEXT_BASE /* use 32 words about stack */ 450 bl hang /* hang and never return */ 451#else /* !CONFIG_SPL_BUILD */ 452 .align 5 453undefined_instruction: 454 get_bad_stack 455 bad_save_user_regs 456 bl do_undefined_instruction 457 458 .align 5 459software_interrupt: 460 get_bad_stack_swi 461 bad_save_user_regs 462 bl do_software_interrupt 463 464 .align 5 465prefetch_abort: 466 get_bad_stack 467 bad_save_user_regs 468 bl do_prefetch_abort 469 470 .align 5 471data_abort: 472 get_bad_stack 473 bad_save_user_regs 474 bl do_data_abort 475 476 .align 5 477not_used: 478 get_bad_stack 479 bad_save_user_regs 480 bl do_not_used 481 482#ifdef CONFIG_USE_IRQ 483 484 .align 5 485irq: 486 get_irq_stack 487 irq_save_user_regs 488 bl do_irq 489 irq_restore_user_regs 490 491 .align 5 492fiq: 493 get_fiq_stack 494 /* someone ought to write a more effiction fiq_save_user_regs */ 495 irq_save_user_regs 496 bl do_fiq 497 irq_restore_user_regs 498 499#else 500 501 .align 5 502irq: 503 get_bad_stack 504 bad_save_user_regs 505 bl do_irq 506 507 .align 5 508fiq: 509 get_bad_stack 510 bad_save_user_regs 511 bl do_fiq 512 513#endif 514 .align 5 515#endif /* CONFIG_SPL_BUILD */ 516 517 518/* 519 * Enable MMU to use DCache as DRAM. 520 * 521 * This is useful on PXA25x and PXA26x in early bootstages, where there is no 522 * other possible memory available to hold stack. 523 */ 524#ifdef CONFIG_CPU_PXA25X 525.macro CPWAIT reg 526 mrc p15, 0, \reg, c2, c0, 0 527 mov \reg, \reg 528 sub pc, pc, #4 529.endm 530lock_cache_for_stack: 531 /* Domain access -- enable for all CPs */ 532 ldr r0, =0x0000ffff 533 mcr p15, 0, r0, c3, c0, 0 534 535 /* Point TTBR to MMU table */ 536 ldr r0, =mmutable 537 mcr p15, 0, r0, c2, c0, 0 538 539 /* Kick in MMU, ICache, DCache, BTB */ 540 mrc p15, 0, r0, c1, c0, 0 541 bic r0, #0x1b00 542 bic r0, #0x0087 543 orr r0, #0x1800 544 orr r0, #0x0005 545 mcr p15, 0, r0, c1, c0, 0 546 CPWAIT r0 547 548 /* Unlock Icache, Dcache */ 549 mcr p15, 0, r0, c9, c1, 1 550 mcr p15, 0, r0, c9, c2, 1 551 552 /* Flush Icache, Dcache, BTB */ 553 mcr p15, 0, r0, c7, c7, 0 554 555 /* Unlock I-TLB, D-TLB */ 556 mcr p15, 0, r0, c10, c4, 1 557 mcr p15, 0, r0, c10, c8, 1 558 559 /* Flush TLB */ 560 mcr p15, 0, r0, c8, c7, 0 561 562 /* Allocate 4096 bytes of Dcache as RAM */ 563 564 /* Drain pending loads and stores */ 565 mcr p15, 0, r0, c7, c10, 4 566 567 mov r4, #0x00 568 mov r5, #0x00 569 mov r2, #0x01 570 mcr p15, 0, r0, c9, c2, 0 571 CPWAIT r0 572 573 /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */ 574 mov r0, #128 575 ldr r1, =0xfffff000 576 577alloc: 578 mcr p15, 0, r1, c7, c2, 5 579 /* Drain pending loads and stores */ 580 mcr p15, 0, r0, c7, c10, 4 581 strd r4, [r1], #8 582 strd r4, [r1], #8 583 strd r4, [r1], #8 584 strd r4, [r1], #8 585 subs r0, #0x01 586 bne alloc 587 /* Drain pending loads and stores */ 588 mcr p15, 0, r0, c7, c10, 4 589 mov r2, #0x00 590 mcr p15, 0, r2, c9, c2, 0 591 CPWAIT r0 592 593 mov pc, lr 594 595.section .mmutable, "a" 596mmutable: 597 .align 14 598 /* 0x00000000 - 0xffe00000 : 1:1, uncached mapping */ 599 .set __base, 0 600 .rept 0xfff 601 .word (__base << 20) | 0xc12 602 .set __base, __base + 1 603 .endr 604 605 /* 0xfff00000 : 1:1, cached mapping */ 606 .word (0xfff << 20) | 0x1c1e 607#endif /* CONFIG_CPU_PXA25X */ 608